component

ISL55110IVZ

Public Made by Adom

by adom

RENESAS Gate Drive ICs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsisl55110ivzfactory-2.0.0extractor-text

Verified ISL55110IVZ

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ISL55110IVZ · TSSOP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C1556088, digikey ISL55110IVZ-ND, mouser 968-ISL55110IVZ
  • ✓family: TSSOP-8_4.4x3mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-oddgq77x/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.18)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ isl55110ivz.kicad_sym✓ isl55110ivz.kicad_mod✓ isl55110ivz.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers isl55110ivz: viewers · Ray 1d ago
isl55110ivz-etched.glb Publish 0.1.0 · Ray 1d ago
isl55110ivz-etched.step isl55110ivz: factory component page (tier=mfr) · Ray 1d ago
isl55110ivz-hero.glb isl55110ivz: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
isl55110ivz-hero.overlay.json Publish 0.1.0 · Ray 1d ago
isl55110ivz.glb Publish 0.1.0 · Ray 1d ago
isl55110ivz.kicad_mod Publish 0.1.0 · Ray 1d ago
isl55110ivz.kicad_sym Publish 0.1.0 · Ray 1d ago
isl55110ivz.lbr Publish 0.1.0 · Ray 1d ago
isl55110ivz.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 1d ago

ISL55110IVZ

RENESAS · Gate Drive ICs · TSSOP-8

ISL55110IVZ from RENESAS, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Logic power supply, specified at 2.7V to 5.5V in the Recommended Operating Conditions.
2 PD input Power-down input; active logic high places the part in power-down mode, with logic high at 2.0V to VDD and logic low at 0V to 0.8V.
3 IN-B input Logic-level input that drives OB to the VH rail or ground, not inverted on the ISL55110.
4 IN-A input Logic-level input that drives OA to the VH rail or ground, not inverted.
5 OA output Driver output related to IN-A, swinging between ground and the VH rail.
6 VH power_in Driver high rail supply, specified at 5V to 13.2V in the Recommended Operating Conditions.
7 GND power_in Ground, return for both the VH rail and the VDD logic supply.
8 OB output Driver output related to IN-B, swinging between ground and the VH rail.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic Input Threshold - Low-to-High VIX_LH 1.32 1.42 1.52 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; IIH = 1µA: VIN-A, VIN-B 4
Logic Input Threshold - High-to-Low VIX_HL 1.12 1.22 1.32 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; IIL = 1µA: VIN-A, VIN-B 4
Logic Input Hysteresis VHYS 0.2 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; VIN-A, VIN-B 4
Logic Input High Threshold (PD) VIH 2 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD 4
Logic Input Low Threshold (PD) VIL 0 0.8 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD 4
Input Current Logic High (VIN-A, VIN-B) IIX_H 10 20 nA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; VIN-A, VIN-B = VDD 4
Input Current Logic Low (VIN-A, VIN-B) IIX_L 10 20 nA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; VIN-A, VIN-B = 0V 4
Input Current Logic High (PD) II_H 10 20 nA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = VDD 4
Input Current Logic Low (PD) II_L 10 15 nA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = 0V 4
Driver Output Resistance rDS 3 6 Ω VH = 12V, VDD = 2.7-5.5V, TA = 25°C; OA, OB 4
Driver Output DC Current (>2s) IDC 100 mA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; >2s 4
Peak Output Current IAC 3.5 A VH = 12V, VDD = 2.7-5.5V, TA = 25°C; Design Intent; verified via simulation 4
Driver Output Swing Range (VOH to VOL) VOH to VOL 3 13.2 V VH = 12V, VDD = 2.7-5.5V, TA = 25°C; OA or OB = "1", voltage referenced to GND 4
Logic Supply Quiescent Current IDD 4 6 mA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = Low 5
Logic Supply Power-down Current IDD-PDN 12 µA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = High 5
Driver Supply Quiescent Current IH 15 µA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = Low, outputs unloaded 5
Driver Supply Power-down Current IH_PDN 2.5 µA VH = 12V, VDD = 2.7-5.5V, TA = 25°C; PD = High 5
Driver Rise Time (100pF/1k) tR 1.2 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 2, OA, OB: CL = 100pF/1k, 10% to 90%, VOH - VOL = 12V 5
Driver Fall Time (100pF/1k) tF 1.4 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 2, OA, OB: CL = 100pF/1k, 10% to 90%, VOH - VOL = 12V 5
Driver Rise Time (1nF) tR 6.2 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 2, OA, OB: CL = 1nF, 10% to 90%, VOH - VOL = 12V 5
Driver Fall Time (1nF) tF 6.9 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 2, OA, OB: CL = 1nF, 10% to 90%, VOH - VOL = 12V 5
Input to Output Propagation Delay, rising (100pF/1k) tpdR 10.9 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, load 100pF/1k 5
Input to Output Propagation Delay, falling (100pF/1k) tpdF 10.7 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, load 100pF/1k 5
Input to Output Propagation Delay, rising (330pF) tpdR 12.8 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, load 330pF 5
Input to Output Propagation Delay, falling (330pF) tpdF 12.5 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, load 330pF 5
Input to Output Propagation Delay, rising (680pF) tpdR 14.5 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, load 680pF 5
Input to Output Propagation Delay, falling (680pF) tpdF 14.1 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, all loads 5
Channel-to-Channel tpdR Spread with Same Loads tSkewR 0.5 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, all loads 5
Channel-to-Channel tpdF Spread with Same Loads tSkewF 0.5 ns VH = 12V, VDD = 3.6V, TA = 25°C; Figure 3, all loads 5
Maximum Operating Frequency FMAX 70 MHz VH = 12V, VDD = 3.6V, TA = 25°C 5
Minimum Pulse Width TMIN 6 ns VH = 12V, VDD = 3.6V, TA = 25°C 5
Power-down to Power-on Time PDEN 650 ns VH = 12V, VDD = 3.6V, TA = 25°C 5
Power-on to Power-down Time PDDIS 40 ns VH = 12V, VDD = 3.6V, TA = 25°C 5
VH to GND 14 V TA = +25°C 4
VDD to GND 6.5 V TA = +25°C 4
Maximum Peak Output Current 300 mA TA = +25°C 4
Maximum Storage Temperature Range -65 150 °C 4
Temperature Range -40 85 °C 4
Drive Supply Voltage (VH) VH 5 13.2 V 4
Logic Supply Voltage (VDD) VDD 2.7 5.5 V 4
Ambient Temperature (TA) TA -40 85 °C 4
Junction Temperature (TJ) TJ 150 °C 4
Maximum Junction Temperature (Plastic Package) 150 °C 4
Thermal Resistance Junction-to-Ambient, 8 Ld TSSOP θJA 140 °C/W Notes 4, 7; measured in free air on high thermal conductivity test board 4
Thermal Resistance Junction-to-Case, 8 Ld TSSOP θJC 46 °C/W Note 7; case temperature at package top center 4

CAD (KiCad official)

  • Symbol: ISL55110IVZ
  • Footprint: Package_SO:TSSOP-8_4.4x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: isl55110ivz-etched.step / isl55110ivz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl55110ivz.step / isl55110ivz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (19 pp, sha256 f894c61e6bc102b1, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF