component

ISL55110IVZ-T

Public Made by Adom

by adom

RENESAS Gate Drive ICs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsisl55110ivz-tfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
isl55110ivz-t / README.md
History Download
Ray Publish 0.1.0 2d8dbb7 15d ago

ISL55110IVZ-T

RENESAS · Gate Drive ICs · TSSOP-8

ISL55110IVZ-T from RENESAS, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Logic power supply, recommended 2.7V to 5.5V (6.5V absolute maximum to GND).
2 PD input Power-down input; active logic high places the part in power-down mode (VIH 2.0V min, VIL 0.8V max).
3 IN-B input Logic level input that drives OB to the VH rail or ground; not inverted on ISL55110, inverted on ISL55111.
4 IN-A input Logic level input that drives OA to the VH rail or ground; not inverted.
5 OA output Driver output related to IN-A, swinging between ground and VH with about 3 ohm typical output resistance.
6 VH power_in Driver high rail supply, recommended 5V to 13.2V (14.0V absolute maximum to GND).
7 GND power_in Ground, return for both the VH rail and the VDD logic supply.
8 OB output Driver output related to IN-B, swinging between ground and VH with about 3 ohm typical output resistance.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic Input Threshold Low-to-High VIX_LH 1.32 1.42 1.52 V lIH = 1µA: VIN-A, VIN-B 4
Logic Input Threshold High-to-Low VIX_HL 1.12 1.22 1.32 V lIL = 1µA: VIN-A, VIN-B 4
Logic Input High Threshold PD VIH 2 V PD (max printed as VDD) 4
Logic Input Low Threshold PD VIL 0 0.8 V PD 4
Driver Output Swing Range VOH to VOL 3 13.2 V OA or OB = "1", voltage referenced to GND 4
Logic Supply Quiescent Current IDD 4 6 mA PD = Low 5
Driver Output Resistance rDS 3 6 Ω OA, OB 4
Driver Output DC Current IDC 100 mA (>2s) 4
Input Current Logic High IIX_H 10 20 nA VIN-A, VIN-B = VDD 4
Input Current Logic Low IIX_L 10 20 nA VIN-A, VIN-B = 0V 4
Input Current Logic Low II_L 10 15 nA PD = 0V 4
Logic Supply Power-down Current IDD-PDN 12 µA PD = High 5
Driver Supply Quiescent Current IH 15 µA PD = Low, outputs unloaded 5
Driver Supply Power-down Current IH_PDN 2.5 µA PD = High 5
Peak Output Current IAC 3.5 A Design Intent; verified via simulation. 4
Logic Input Hysteresis VHYS 0.2 V VIN-A, VIN-B 4
Channel-to-Channel tpdR Spread tSkewR 0.5 ns Figure 3, All loads (<0.5) 5
Channel-to-Channel tpdF Spread tSkewF 0.5 ns Figure 3, All loads (<0.5) 5
Maximum Operating Frequency FMAX 70 MHz 5
Minimum Pulse Width TMIN 6 ns 5
Driver Rise Time tR 1.2 ns Figure 2, OA, OB: CL = 100pF/1k 10% to 90%, VOH - VOL = 12V 5
Driver Fall Time tF 1.4 ns Figure 2, OA, OB: CL = 100pF/1k 10% to 90%, VOH - VOL = 12V 5
Driver Rise Time tR 6.2 ns Figure 2, OA, OB: CL = 1nF 10% to 90%, VOH - VOL = 12V 5
Driver Fall Time tF 6.9 ns Figure 2, OA, OB: CL = 1nF 10% to 90%, VOH - VOL = 12V 5
Input to Output Propagation Delay (rise) tpdR 10.9 ns Figure 3, load 100pF/1k 5
Input to Output Propagation Delay (fall) tpdF 10.7 ns Figure 3, load 100pF/1k 5
Input to Output Propagation Delay (rise) tpdR 12.8 ns Figure 3, load 330pF 5
Input to Output Propagation Delay (fall) tpdF 12.5 ns Figure 3, load 330pF 5
Input to Output Propagation Delay (rise) tpdR 14.5 ns Figure 3, load 680pF 5
Input to Output Propagation Delay (fall) tpdF 14.1 ns Figure 3, load 680pF 5
Power-down to Power-on Time PDEN 650 ns 5
Power-on to Power-down Time PDDIS 40 ns 5
VH to GND VH 14 V TA = +25°C 4
VDD to GND VDD 6.5 V TA = +25°C 4
Maximum Peak Output Current 300 mA TA = +25°C 4
ESD Rating Human Body Model 3 kV 4
Maximum Junction Temperature (Plastic Package) TJ 150 °C 4
Storage Temperature Range -65 150 °C 4
Drive Supply Voltage VH 5 13.2 V 4
Logic Supply Voltage VDD 2.7 5.5 V 4
Ambient Temperature TA -40 85 °C 4
Thermal Resistance Junction to Ambient, 8 Ld TSSOP θJA 140 °C/W Notes 4, 7 4
Thermal Resistance Junction to Case, 8 Ld TSSOP θJC 46 °C/W Notes 4, 7 4

CAD (KiCad official)

  • Symbol: ISL55110IVZ-T
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: isl55110ivz-t-etched.step / isl55110ivz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl55110ivz-t.step / isl55110ivz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (19 pp, sha256 f894c61e6bc102b1, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF