# ISL43485IBZ-T

**RENESAS** · Pre-ordered Chips · SOIC-8

ISL43485IBZ-T from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output: high if A > B by at least 0.2V, low if A < B by 0.2V or more, high if A and B are floating; high impedance when RE is high. |
| 2 | RE | input | Receiver output enable: RO is enabled when RE is low and high impedance when RE is high; logic input accepts up to 7V (abs max). |
| 3 | DE | input | Driver output enable: driver outputs Y and Z are enabled when DE is high and high impedance when DE is low; logic input accepts up to 7V (abs max). |
| 4 | DI | input | Driver input: a low forces Y low and Z high, a high forces Y high and Z low; logic input accepts up to 7V (abs max). |
| 5 | GND | power_in | Ground connection. |
| 6 | A/Y | bidirectional | Noninverting receiver input and noninverting driver output; input if DE = 0, output if DE = 1, with -8V to +12.5V abs max range. |
| 7 | B/Z | bidirectional | Inverting receiver input and inverting driver output; input if DE = 0, output if DE = 1, with -8V to +12.5V abs max range. |
| 8 | VCC | power_in | System power supply input (3V to 3.6V), 7V absolute maximum to ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 3 |  | 3.6 | V | VCC = 3V to 3.6V | 3 |
| Operating temperature |  | -40 |  | 85 | °C |  | 3 |
| VCC to Ground | VCC |  |  | 7 | V |  | 3 |
| Input voltage DI, DE, RE |  | -0.5 |  | 7 | V |  | 3 |
| Input/output voltage A/Y, B/Z |  | -8 |  | 12.5 | V |  | 3 |
| Output voltage RO |  | -0.5 |  |  | V | -0.5V to (VCC +0.5V) | 3 |
| Maximum junction temperature |  |  |  | 150 | °C | Plastic package | 3 |
| Storage temperature |  | -65 |  | 150 | °C |  | 3 |
| Lead temperature |  |  |  | 300 | °C | Soldering 10s, lead tips only | 3 |
| Driver differential VOUT (with load) | VOD2 | 2 | 2.7 |  | V | RL = 100Ω (RS-422) (Figure 1A), Full | 3 |
| Driver differential VOUT (with load) | VOD2 | 1.5 | 2.3 |  | V | RL = 54Ω (RS-485) (Figure 1A), Full | 3 |
| Driver differential VOUT (with load) | VOD2 | 1.5 | 2.6 |  | V | RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure 1B), Full | 3 |
| Change in magnitude of driver differential VOUT | ΔVOD |  | 0.01 | 0.2 | V | RL = 54Ω or 100Ω (Figure 1A), Full | 3 |
| Driver common-mode VOUT | VOC |  | 1.8 | 3 | V | RL = 54Ω or 100Ω (Figure 1A), Full | 3 |
| Change in magnitude of driver common-mode VOUT | ΔVOC |  | 0.01 | 0.2 | V | RL = 54Ω or 100Ω (Figure 1A), Full | 3 |
| Logic input high voltage | VIH | 2 |  |  | V | DE, DI, RE, Full | 3 |
| Logic input low voltage | VIL |  |  | 0.8 | V | DE, DI, RE, Full | 3 |
| Logic input current | IIN1 | -2 |  | 2 | µA | DE, DI, Full | 3 |
| Logic input current | IIN1 | -25 |  | 25 | µA | RE, Full | 3 |
| Input current (A/Y, B/Z) | IIN2 |  | 0.6 | 1 | mA | DE = 0V, VCC = 0V or 3.6V, VIN = 12V, Full | 3 |
| Input current (A/Y, B/Z) | IIN2 |  | -0.3 | -0.8 | mA | DE = 0V, VCC = 0V or 3.6V, VIN = -7V, Full | 3 |
| Receiver differential threshold voltage | VTH | -0.2 |  | 0.2 | V | -7V ≤ VCM ≤ 12V, Full | 3 |
| Receiver output low voltage | VOL |  |  | 0.4 | V | IO = -4mA, VID = 200mV, Full | 3 |
| Three-state receiver output current | IOZR | -1 |  | 1 | µA | 0.4V ≤ VO ≤ 2.4V, Full | 4 |
| Receiver input resistance | RIN | 12 | 19 |  | kΩ | -7V ≤ VCM ≤ 12V, Full | 4 |
| No-load supply current | ICC |  | 0.75 | 1.2 | mA | DI = 0V or VCC, DE = VCC, RE = 0V or VCC, Full | 4 |
| No-load supply current | ICC |  | 0.65 | 1 | mA | DI = 0V or VCC, DE = 0V, RE = 0V, Full | 4 |
| Shutdown supply current | ISHDN |  | 15 | 100 | nA | DE = 0V, RE = VCC, DI = 0V or VCC, Full | 4 |
| Driver short-circuit current | IOSD1 |  |  | 250 | mA | DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 7), Full | 4 |
| Receiver short-circuit current | IOSR | 8 |  | 60 | mA | 0V ≤ VO ≤ VCC, Full | 4 |
| Driver maximum data rate | fMAX | 30 | 50 |  | Mbps | (Figure 2A), Full | 4 |
| Driver differential output delay | tDD | 3 | 10 | 25 | ns | RDIFF = 60Ω, CL = 15pF (Figure 2A), Full | 4 |
| Driver differential rise or fall time | tR, tF | 3 | 6 | 12 | ns | RDIFF = 60Ω, CL = 15pF (Figure 2A), Full | 4 |
| Driver input to output delay | tPLH, tPHL | 6 | 10 | 22 | ns | RL = 27Ω, CL = 15pF (Figure 2C), Full | 4 |
| Driver output skew | tSKEW |  | 1 | 5 | ns | RL = 27Ω, CL = 15pF (Figure 2C), Full | 4 |
| Driver enable to output high | tZH |  | 45 | 90 | ns | RL = 110Ω, CL = 50pF, SW = GND (Figure 3), (Note 8), Full | 4 |
| Driver enable to output low | tZL |  | 45 | 90 | ns | RL = 110Ω, CL = 50pF, SW = VCC (Figure 3), (Note 8), Full | 4 |
| Driver disable from output high | tHZ |  | 60 | 90 | ns | RL = 110Ω, CL = 50pF, SW = GND (Figure 3), Full | 4 |
| Driver disable from output low | tLZ |  | 70 | 100 | ns | RL = 110Ω, CL = 50pF, SW = VCC (Figure 3), Full | 4 |
| Driver enable from shutdown to output high | tZH(SHDN) |  | 115 | 150 | ns | RL = 110Ω, CL = 50pF, SW = GND (Figure 3), (Notes 10, 11), Full | 4 |
| Driver enable from shutdown to output low | tZL(SHDN) |  | 115 | 150 | ns | RL = 110Ω, CL = 50pF, SW = VCC (Figure 3), (Notes 10, 11), Full | 4 |
| Receiver maximum data rate | fMAX | 27 | 35 |  | Mbps | VID ≥ 1.5V with tr/tf = 10ns, RO tH & tL ≥ 60% tUI (Figure 4), Full | 4 |
| Receiver input to output delay | tPLH, tPHL | 25 | 45 | 80 | ns | (Figure 4), Full | 4 |
| Receiver skew /tPLH - tPHL/ | tSKD |  | 2 | 12 | ns | (Figure 4), Full | 4 |
| Receiver enable to output high | tZH |  | 11 | 25 | ns | RL = 1kΩ, CL = 15pF, SW = GND (Figure 5), (Note 9), Full | 4 |
| Receiver enable to output low | tZL |  | 11 | 25 | ns | RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5), (Note 9), Full | 4 |
| Receiver disable from output high | tHZ |  | 7 | 20 | ns | RL = 1kΩ, CL = 15pF, SW = GND (Figure 5), Full | 4 |
| Receiver disable from output low | tLZ |  | 7 | 20 | ns | RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5), Full | 5 |
| Time to shutdown | tSHDN | 80 | 190 | 300 | ns | (Note 10), Full | 5 |
| Receiver enable from shutdown to output high | tZH(SHDN) |  | 240 | 400 | ns | RL = 1kΩ, CL = 15pF, SW = GND (Figure 5), (Notes 10, 12), Full | 5 |
| Receiver enable from shutdown to output low | tZL(SHDN) |  | 240 | 400 | ns | RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5), (Notes 10, 12), Full | 5 |
| Receiver input hysteresis | VTH |  | 50 |  | mV | VCM = 0V, +25°C | 3 |
| Thermal resistance, 8 Ld SOIC | θJA |  | 170 |  | °C/W | Typical, Note 4 | 3 |

## CAD (KiCad official)

- Symbol: `ISL43485IBZ-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `isl43485ibz-t-etched.step` / `isl43485ibz-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isl43485ibz-t.step` / `isl43485ibz-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/isl43485ibz-t-datasheet.pdf) (13 pp, sha256 `865b85e99da3f01d`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/isl43485ibz-t-datasheet.pdf)