component
ISL22326WFV14Z-TK
Public Made by Adomby adom
RENESAS Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 7d ago |
| viewers | 7d ago |
| isl22326wfv14z-tk-etched.glb | 7d ago |
| isl22326wfv14z-tk-etched.step | 7d ago |
| isl22326wfv14z-tk-hero.glb | 7d ago |
| isl22326wfv14z-tk-hero.overlay.json | 7d ago |
| isl22326wfv14z-tk.glb | 7d ago |
| isl22326wfv14z-tk.kicad_mod | 7d ago |
| isl22326wfv14z-tk.kicad_sym | 7d ago |
| isl22326wfv14z-tk.lbr | 7d ago |
| isl22326wfv14z-tk.step | 7d ago |
| package.json | 7d ago |
| page.json | 7d ago |
| README.md | 7d ago |
| verification.json | 7d ago |
ISL22326WFV14Z-TK
RENESAS · Digital Potentiometers · TSSOP-14
ISL22326WFV14Z-TK from RENESAS, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Power supply pin; the recommended operating VCC range is 2.7V to 5.5V. |
| 2 | SHDN | input | Active-low shutdown input that forces RH to an open circuit and shorts RW to RL; it must remain HIGH for normal operation. |
| 3 | RH0 | passive | "High" terminal of DCP0, equivalent to the fixed high end of a mechanical potentiometer. |
| 4 | RL0 | passive | "Low" terminal of DCP0, equivalent to the fixed low end of a mechanical potentiometer. |
| 5 | RW0 | passive | "Wiper" terminal of DCP0, equivalent to the movable terminal of a mechanical potentiometer. |
| 6 | A2 | input | Device address input that sets the least significant bit 2 of the 7-bit I2C slave address; up to 8 devices may share the bus. |
| 7 | SCL | input | Open-drain I2C serial clock input that requires an external pull-up resistor. |
| 8 | SDA | bidirectional | Open-drain I2C serial data input/output that requires an external pull-up resistor. |
| 9 | GND | power_in | Device ground pin. |
| 10 | RW1 | passive | "Wiper" terminal of DCP1, equivalent to the movable terminal of a mechanical potentiometer. |
| 11 | RL1 | passive | "Low" terminal of DCP1, equivalent to the fixed low end of a mechanical potentiometer. |
| 12 | RH1 | passive | "High" terminal of DCP1, equivalent to the fixed high end of a mechanical potentiometer. |
| 13 | A0 | input | Device address input that sets the least significant bit 0 of the 7-bit I2C slave address. |
| 14 | A1 | input | Device address input that sets bit 1 of the 7-bit I2C slave address. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| RH to RL Resistance (W option) | RTOTAL | 10 | kΩ | W option | 4 | ||
| RH to RL Resistance Tolerance | -20 | 20 | % | W and U option | 4 | ||
| End-to-End Temperature Coefficient | 50 | ppm/°C | W option (±50) | 4 | |||
| Wiper Resistance | RW | 70 | 200 | Ω | VCC = 3.3V, wiper current = VCC/RTOTAL | 4 | |
| VRH and VRL Terminal Voltages | VRH, VRL | 0 | V | VRH and VRL to GND; max VCC | 4 | ||
| Leakage on DCP Pins | ILkgDCP | 0.1 | 1 | µA | Voltage at pin from GND to VCC | 4 | |
| Integral Non-linearity (voltage divider) | INL | -1 | 1 | LSB | Monotonic over all tap positions, W and U option | 4 | |
| Differential Non-linearity (voltage divider) | DNL | -0.5 | 0.5 | LSB | Monotonic over all tap positions, W and U option | 4 | |
| Zero-scale Error (W option) | ZSerror | 0 | 1 | 5 | LSB | W option | 4 |
| Full-scale Error (W option) | FSerror | -5 | -1 | 0 | LSB | W option | 4 |
| DCP to DCP Matching (voltage divider) | VMATCH | -2 | 2 | LSB | Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals | 4 | |
| Ratiometric Temperature Coefficient | TCV | 4 | ppm/°C | DCP register set to 40 hex (±4) | 4 | ||
| Integral Non-linearity (resistor mode) | RINL | -1 | 1 | MI | DCP register set between 10h and 7Fh; monotonic over all tap positions | 5 | |
| Differential Non-linearity (resistor mode, W option) | RDNL | -1 | 1 | MI | DCP register set between 10h and 7Fh; monotonic over all tap positions, W option | 5 | |
| Offset (W option) | Roffset | 0 | 1 | 5 | MI | W option | 5 |
| DCP to DCP Matching (resistor mode) | RMATCH | -2 | 2 | MI | Any two DCPs at the same tap position with the same terminal voltages | 5 | |
| VCC Supply Current (Volatile Write/Read) | ICC1 | 0.5 | mA | fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) | 5 | ||
| VCC Supply Current (Non-volatile Write/Read) | ICC2 | 3 | mA | fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) | 5 | ||
| VCC Current (Standby) | ISB | 5 | µA | VCC = +5.5V @ +85°C, I2C interface in standby state | 5 | ||
| VCC Current (Standby) | ISB | 7 | µA | VCC = +5.5V @ +125°C, I2C interface in standby state | 5 | ||
| VCC Current (Standby) | ISB | 3 | µA | VCC = +3.6V @ +85°C, I2C interface in standby state | 5 | ||
| VCC Current (Shutdown) | ISD | 3 | µA | VCC = +5.5V @ +85°C, I2C interface in standby state | 5 | ||
| VCC Current (Shutdown) | ISD | 5 | µA | VCC = +5.5V @ +125°C, I2C interface in standby state | 5 | ||
| VCC Current (Shutdown) | ISD | 2 | µA | VCC = +3.6V @ +85°C, I2C interface in standby state | 5 | ||
| VCC Current (Shutdown) | ISD | 4 | µA | VCC = +3.6V @ +125°C, I2C interface in standby state | 5 | ||
| Leakage Current at Digital Pins | ILkgDig | -1 | 1 | µA | Voltage at pin from GND to VCC | 5 | |
| DCP Wiper Response Time | tWRT | 1.5 | µs | SCL falling edge of last bit of DCP data byte to wiper new position | 5 | ||
| DCP Recall Time from Shutdown Mode | tShdnRec | 1.5 | µs | From rising edge of SHDN signal to wiper stored position and RH connection | 5 | ||
| Power-on Recall Voltage | Vpor | 2 | 2.6 | V | Minimum VCC at which memory recall occurs | 5 | |
| VCC Ramp Rate | VccRamp | 0.2 | V/ms | 5 | |||
| Power-up Delay | tD | 3 | ms | VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state | 6 | ||
| EEPROM Endurance | 1e+06 | Cycles | 6 | ||||
| EEPROM Retention | 50 | Years | T < +55°C | 6 | |||
| Non-volatile Write Cycle Time | tWC | 12 | 20 | ms | 6 | ||
| Input Buffer LOW Voltage | VIL | -0.3 | 0.3 | V | A2, A1, A0, SHDN, SDA, and SCL; max 0.3*VCC | 6 | |
| Input Buffer HIGH Voltage | VIH | 0.7 | 0.3 | V | A2, A1, A0, SHDN, SDA, and SCL; min 0.7*VCC, max VCC + 0.3 | 6 | |
| SDA Output Buffer LOW Voltage | VOL | 0 | 0.4 | V | Sinking 4mA | 6 | |
| SCL Frequency | fSCL | 400 | kHz | 6 | |||
| Pulse Width Suppression Time | tsp | 50 | ns | Any pulse narrower than the max spec is suppressed | 6 | ||
| SCL falling edge to SDA output data valid | tAA | 900 | ns | SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window | 6 | ||
| Bus Free Time | tBUF | 1300 | ns | SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition | 6 | ||
| Clock LOW Time | tLOW | 1300 | ns | Measured at the 30% of VCC crossing | 6 | ||
| Clock HIGH Time | tHIGH | 600 | ns | Measured at the 70% of VCC crossing | 6 | ||
| START Condition Setup Time | tSU:STA | 600 | ns | SCL rising edge to SDA falling edge; both crossing 70% of VCC | 6 | ||
| START Condition Hold Time | tHD:STA | 600 | ns | From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC | 6 | ||
| Input Data Setup Time | tSU:DAT | 100 | ns | From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC | 6 | ||
| Input Data Hold Time | tHD:DAT | 0 | ns | From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window | 6 | ||
| STOP Condition Setup Time | tSU:STO | 600 | ns | From SCL rising edge crossing 70% of VCC to SDA rising edge crossing 30% of VCC | 6 | ||
| STOP Condition Hold Time for Read, or Volatile Only Write | tHD:STO | 1300 | ns | From SDA rising edge to SCL falling edge; both crossing 70% of VCC | 6 | ||
| Output Data Hold Time | tDH | 0 | ns | From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window | 6 | ||
| SDA and SCL Rise Time | tR | 250 | ns | From 30% to 70% of VCC; min 20 + 0.1*Cb | 6 | ||
| SDA and SCL Fall Time | tF | 250 | ns | From 70% to 30% of VCC; min 20 + 0.1*Cb | 6 | ||
| Capacitive Loading of SDA or SCL | Cb | 10 | 400 | pF | Total on-chip and off-chip | 7 | |
| A2, A1 and A0 Setup Time | tSU:A | 600 | ns | Before START condition | 7 | ||
| A2, A1 and A0 Hold Time | tHD:A | 600 | ns | After STOP condition | 7 | ||
| Supply Voltage | VCC | 2.7 | 5.5 | V | 4 | ||
| Operating Temperature Range (Extended Industrial) | -40 | 125 | °C | 4 | |||
| Storage Temperature | -65 | 150 | °C | 4 | |||
| VCC | VCC | -0.3 | 6 | V | 4 | ||
| Voltage at any DCP Pin with Respect to GND | -0.3 | V | max VCC | 4 | |||
| Wiper Current IW (10s) | IW | -6 | 6 | mA | 10s | 4 | |
| Thermal Resistance Junction-Ambient, 14 Lead TSSOP | θJA | 100 | °C/W | Typical | 4 |
CAD (KiCad official)
- Symbol:
ISL22326WFV14Z-TK - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
isl22326wfv14z-tk-etched.step/isl22326wfv14z-tk-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl22326wfv14z-tk.step/isl22326wfv14z-tk.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (17 pp, sha256
c9b118b955a271de, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).