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ISL2111BR4Z
Public Made by Adomby adom
RENESAS Pre-ordered Chips, DFN-8-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownISL2111BR4Z
RENESAS · Pre-ordered Chips · DFN-8-EP(4x4)
ISL2111BR4Z from RENESAS, in a DFN-8-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply to the lower gate driver, bypassed to VSS, with a recommended operating range of 8V to 14V. |
| 2 | HB | power_in | High-side bootstrap supply; the positive side of the external bootstrap capacitor connects here, and the bootstrap diode is on-chip. |
| 3 | HO | output | High-side output that connects to the gate of the high-side power MOSFET. |
| 4 | HS | passive | High-side source connection to the source of the high-side power MOSFET and the negative side of the bootstrap capacitor, recommended -1V to 100V continuous. |
| 5 | HI | input | High-side logic input, with 3.3V/TTL compatible thresholds on the ISL2111. |
| 6 | LI | input | Low-side logic input, with 3.3V/TTL compatible thresholds on the ISL2111. |
| 7 | VSS | power_in | Chip negative supply, which will generally be ground. |
| 8 | LO | output | Low-side output that connects to the gate of the low-side power MOSFET. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | DFN-8-EP(4x4) |
| Category | Interface ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Quiescent Current | IDD | 0.3 | 0.55 | mA | ISL2111; LI = HI = 0V | 6 | |
| VDD Operating Current | IDDO | 3.5 | 5.5 | mA | ISL2111; f = 500kHz | 6 | |
| Total HB Quiescent Current | IHB | 0.1 | 0.2 | mA | LI = HI = 0V | 6 | |
| Total HB Operating Current | IHBO | 3.4 | 5.5 | mA | f = 500kHz | 6 | |
| HB to VSS Current, Quiescent | IHBS | 0.05 | 10 | µA | LI = HI = 0V; VHB = VHS = 114V | 6 | |
| Low Level Input Voltage Threshold | VIL | 1.2 | 1.8 | V | ISL2111 | 6 | |
| High Level Input Voltage Threshold | VIH | 1.8 | 2.4 | V | ISL2111 | 6 | |
| Input Pull-Down Resistance | RI | 100 | 210 | 500 | kΩ | 7 | |
| VDD Rising Threshold | VDDR | 5.8 | 6.6 | 7.4 | V | 7 | |
| HB Rising Threshold | VHBR | 5 | 6.1 | 7.1 | V | 7 | |
| Low Current Forward Voltage | VDL | 0.5 | 0.7 | V | IVDD-HB = 100µA | 7 | |
| High Current Forward Voltage | VDH | 0.7 | 1 | V | IVDD-HB = 100mA | 7 | |
| Dynamic Resistance | RD | 0.7 | 1.5 | Ω | IVDD-HB = 100mA | 7 | |
| Low Level Output Voltage (LO) | VOLL | 0.1 | 0.25 | V | ILO = 100mA | 7 | |
| High Level Output Voltage (LO) | VOHL | 0.16 | 0.3 | V | ILO = -100mA, VOHL = VDD - VLO | 7 | |
| Low Level Output Voltage (HO) | VOLH | 0.1 | 0.25 | V | IHO = 100mA | 7 | |
| High Level Output Voltage (HO) | VOHH | 0.16 | 0.3 | V | IHO = -100mA, VOHH = VHB - VHO | 7 | |
| Lower Turn-Off Propagation Delay (LI Falling to LO Falling) | tLPHL | 32 | 60 | ns | 7 | ||
| Upper Turn-Off Propagation Delay (HI Falling to HO Falling) | tHPHL | 32 | 60 | ns | 7 | ||
| Lower Turn-On Propagation Delay (LI Rising to LO Rising) | tLPLH | 39 | 60 | ns | 7 | ||
| Upper Turn-On Propagation Delay (HI Rising to HO Rising) | tHPLH | 38 | 60 | ns | 7 | ||
| Delay Matching: Upper Turn-Off to Lower Turn-On | tMON | 8 | 16 | ns | 7 | ||
| Delay Matching: Lower Turn-Off to Upper Turn-On | tMOFF | 6 | 16 | ns | 7 | ||
| Either Output Rise Time (3V to 9V) | tR | 0.3 | 0.5 | µs | CL = 0.1µF | 7 | |
| Either Output Fall Time (9V to 3V) | tF | 0.19 | 0.4 | µs | CL = 0.1µF | 7 | |
| Minimum Input Pulse Width that Changes the Output | tPW | 50 | ns | 7 | |||
| Supply Voltage, VDD, VHB - VHS | VDD | -0.3 | 18 | V | Notes 4, 5 | 6 | |
| LI and HI Voltages | LI, HI | -0.3 | V | Maximum is VDD + 0.3V (Note 5) | 6 | ||
| Voltage on LO | LO | -0.3 | V | Maximum is VDD + 0.3V (Note 5) | 6 | ||
| Voltage on HO relative to HS | HO-HS | -2 | V | Repetitive Transient < 100ns | 6 | ||
| Voltage on LO relative to GND | LO | -2 | V | Repetitive Transient < 100ns | 6 | ||
| Voltage on HS (Continuous) | HS | -1 | 110 | V | Note 5 | 6 | |
| Voltage on HB | HB | 118 | V | Note 5 | 6 | ||
| Average Current in VDD to HB Diode | 100 | mA | 6 | ||||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature Range | TJ | -55 | 150 | °C | 6 | ||
| Supply Voltage, VDD | VDD | 8 | 14 | V | 6 | ||
| Voltage on HS | HS | -1 | 100 | V | 6 | ||
| Voltage on HS (Repetitive Transient < 100ns) | HS | -5 | 105 | V | Repetitive Transient < 100ns | 6 | |
| Voltage on HB above HS | HB-HS | 7 | 14 | V | VHS+7V to VHS+14V | 6 | |
| Voltage on HB relative to VDD | HB-VDD | -1 | 100 | V | VDD - 1V to VDD+100V | 6 | |
| HS Slew Rate | 50 | V/ns | <50V/ns | 6 | |||
| Max Power Dissipation at +25°C in Free Air, 8 Ld DFN | 3.1 | W | 8 Ld DFN (Notes 7, 8) | 6 | |||
| Thermal Resistance, Junction to Ambient, 8 Ld DFN | JA | 40 | °C/W | 8 Ld DFN (Notes 7, 8) | 6 | ||
| Thermal Resistance, Junction to Case, 8 Ld DFN | JC | 4 | °C/W | 8 Ld DFN (Notes 7, 8) | 6 |
CAD (KiCad official)
- Symbol:
ISL2111BR4Z - Footprint:
Package_DFN_QFN:DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm - 3D model: DFN-8-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
isl2111br4z-etched.step/isl2111br4z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl2111br4z.step/isl2111br4z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (17 pp, sha256
5040c7f465690f8c, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).