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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

ISD3900FYI

Nuvoton Tech · Audio Interface ICs · LQFP-48(7x7)

ISD3900FYI from Nuvoton Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	This pin should be left unconnected.
2	CSB	output	Chip Select Bar of the external serial flash interface.
3	DI	input	Serial data input to the external serial flash interface, connected to the flash memory data output (DO).
4	I2S_SDI/GPIO7	input	Serial Data Input of the I2S interface; should be grounded if I2S is not used, or it can be configured as GPIO7.
5	I2S_SCK/GPIO6	bidirectional	I2S clock input in slave mode or clock output in master mode; should be grounded if I2S is not used, or it can be configured as an external clock buffer or as GPIO6.
6	I2S_WS/GPIO5	bidirectional	I2S Word Select input in slave mode or output in master mode; should be grounded if I2S is not used, or it can be configured as GPIO5.
7	I2S_SDO/GPIO4	output	Serial Data Output of the I2S interface; should be left unconnected if I2S is not used, or it can be configured as GPIO4.
8	NC	unconnected	This pin should be left unconnected.
9	NC	unconnected	This pin should be left unconnected.
10	VSSD	power_in	Digital ground.
11	VCCD	power_in	Digital power supply (VDD 2.7V to 3.6V per operating conditions).
12	VREG	power_out	A 1.8V regulator output supplying the internal logic; a 0.1uF capacitor should be connected to this pin for supply decoupling and stability.
13	MISO	output	Master-In-Slave-Out serial output from the ISD3900 to the host; tri-state when SSB=1.
14	SCLK	input	Serial clock input to the ISD3900 from the host.
15	SSB	input	Slave select input from the host; when low the device is selected and responds to SPI commands.
16	MOSI	input	Master-Out-Slave-In serial input to the ISD3900 from the host.
17	VCCD_PWM	power_in	Digital power for the PWM driver.
18	SPK+	output	PWM driver positive output that, with SPK-, drives an 8 ohm speaker or buzzer differentially; tri-state during power down; can alternatively be configured as BTL or independently switched to AUDOUT or AUXOUT.
19	VSSD_PWM	power_in	Digital ground for the PWM driver.
20	SPK-	output	PWM driver negative output that, with SPK+, drives an 8 ohm speaker or buzzer differentially; tri-state during power down; can alternatively be configured as BTL or independently switched to AUDOUT or AUXOUT.
21	VCCD_PWM	power_in	Digital power for the PWM driver.
22	NC	unconnected	This pin should be left unconnected.
23	NC	unconnected	This pin should be left unconnected.
24	NC	unconnected	This pin should be left unconnected.
25	INTB	output	Active-low interrupt request pin; open-drain output.
26	RDY/BSYB	output	Reports the status of SPI data transfer; high indicates the ISD3900 is ready to accept new SPI commands or data.
27	RESET	input	Applying power to this pin resets the chip; a high pulse of 50ms or more will reset the chip.
28	DO	output	Serial data output of the external serial flash interface, connected to the flash data input (DI).
29	CLK	output	Serial data clock of the external serial flash interface.
30	GPIO3	bidirectional	General-purpose I/O pin.
31	GPIO2	bidirectional	General-purpose I/O pin.
32	GPIO1	bidirectional	General-purpose I/O pin.
33	NC	unconnected	This pin should be left unconnected.
34	NC	unconnected	This pin should be left unconnected.
35	XTALOUT	output	Crystal interface output pin.
36	XTALIN	input	Depending on the CLK_CFG register, connects to a crystal/resonator with XTALOUT, to a GND-referenced resistor as oscillator reference current (XTALOUT left unconnected), or to an external clock input (XTALOUT left unconnected).
37	NC	unconnected	This pin should be left unconnected.
38	GPIO0	bidirectional	General-purpose I/O pin.
39	NC	unconnected	This pin should be left unconnected.
40	NC	unconnected	This pin should be left unconnected.
41	AUDOUT	output	Audio output configurable by SPI command as a voltage or current output; leave unconnected if not used.
42	AUXOUT	output	Aux output, an analog voltage output; leave unconnected if not used.
43	VCCA	power_in	Analog power supply pin.
44	VSSA	power_in	Analog ground pin.
45	ANAOUT/MIC-	output	Variable gain analog output with gain set by feedback resistance to ANAIN, or configurable as MIC- with MIC+ for a differential microphone input; leave unconnected if ANAIN/ANAOUT is not used.
46	ANAIN/MIC+	input	Variable gain analog input, or configurable as MIC+ with MIC- for a differential microphone input; leave unconnected if ANAIN/ANAOUT is not used.
47	AUXIN	input	Auxiliary input with gain set by SPI command; leave unconnected if not used.
48	NC	unconnected	This pin should be left unconnected.

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	LQFP-48(7x7)
Category	Communication Interface Chip/UART/485/232
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VDD	2.7		3.6	V		11
Operating temperature range (Case temperature)		-40		85	°C		11
Input voltage (VDD)		0		3.6	V		11
Power supply voltage to ground potential		-0.3		5	V		11
Supply Voltage	VDD	2.7		3.6	V		11
INTB Output Low Voltage	VOH1			0.4	V		11
Record Current	IDD_Record			40	mA	VDD= 3.6V, No load, Sampling freq = 16 kHz	11
Playback Current	IDD_Playback			30	mA		11
Standby Current	ISB		1	10	µA	VDD= 3.6V	11
Internal oscillator frequency deviation, internal reference (nominal 2.048 MHz)	FINT	-10		10	%	Vdd = 3V. At room temperature	13
Internal oscillator frequency deviation, external 78.7kohm resistor (nominal 2.048 MHz)	FExt	-5		5	%	With 1% precision resistor, 78.7kohm. Vdd = 3V. At room temperature	13
ANAIN Input Voltage	VANAIN	10		1000	mV	Peak-to-Peak; [2] Depends on Gain Setting	13
ANAIN Feed Back Resistance	RANA(FB)	40		100	KΩ	Conditions VDD=3V, TA=25°C unless otherwise stated (table note [1])	13
MICIN Input Voltage	VMICIN	5		500	mV	Peak-to-Peak; [2] Depends on Gain Setting	13
Gain from AUXIN to AUXOUT/ANAOUT	AAUXIN GAIN	0		9	dB	4 Gain Steps of 3db each	13
AUXIN Gain Accuracy	AAUXIN (GA)	-0.5		0.5	dB		13
AUXIN Input Resistance	RAUXIN	20		40	KΩ	Depending on AUXIN Gain Setting	13
Minimum Load Impedance (AUXOUT)	RL(AUXOUT)	5			KΩ		14
Maximum Load Capacitance (AUXOUT)	CL(AUXOUT)			0.1	nF		14
Minimum Load Impedance (AUDOUT)	RL(AUDOUT)	5			KΩ	Configured as AUDOUT (Voltage Output)	14
Maximum Load Capacitance (AUDOUT)	CL(AUDOUT)			0.1	nF	Configured as AUDOUT (Voltage Output)	14
Output Current (AUDOUT)	IAUDOUT	0	3	6	mA	[2] 1 Vpp 1KHz signal at AUXIN/ANAIN, 0db Gain; [6] Configured as AUDOUT(Current Output)	14
THD, AUXIN to SPK+/SPK-	THD			1	%	Load 8Ω [2]	15
Minimum Load Impedance (SPK)	RL(SPK)	4			Ω		15
SCLK Cycle Time	TSCK	60			ns		15
SCLK High Pulse Width	TSCKH	25			ns		15
SCLK Low Pulse Width	TSCKL	25			ns		15
Rise Time for All Digital Signals	TRISE			10	ns		15
Fall Time for All Digital Signals	TFALL			10	ns		16
SSB Falling Edge to 1st SCLK Falling Edge Setup Time	TSSBS	30			ns		16
Last SCLK Rising Edge to SSB Rising Edge Hold Time	TSSBH	30		50	ns (min), us (max)		16
SSB High Time between SSB Lows	TSSBHI	20			ns		16
MOSI to SCLK Rising Edge Setup Time	TMOS	15			ns		16
SCLK Rising Edge to MOSI Hold Time	TMOH	15			ns		16
Delay Time from SSB Falling Edge to MISO Active	TZMID			12	ns		16
Delay Time from SSB Rising Edge to MISO Tri-state	TMIZD			12	ns		16
Delay Time from SCLK Falling Edge to MISO	TMID			12	ns		16
Delay Time from SCLK Rising Edge to RDY/BSYB Falling Edge	TCRBD			12	ns		16
Delay Time from RDY/BSYB Rising Edge to SCLK Falling Edge	TRBCD	0			ns		16
IS_SCK Cycle Time	TSCK	60			ns		17
IS_SCK High Pulse Width	TSCKH	25			ns		17
IS_SCK Low Pulse Width	TSCKL	25			ns		17
Rise Time for All Digital Signals	TRISE			10	ns		17
Fall Time for All Digital Signals	TFALL			10	ns		17
WS to IS_SCK Rising Edge Setup Time	TWSS	20			ns		17
IS_SCK Rising Edge to IS_WS Hold Time	TWSH	20			ns		17
IS_SDI to IS_SCK Rising Edge Setup Time	TSDIS	15			ns		17
IS_SCK Rising Edge to IS_SDI Hold Time	TSDIH	15			ns		17
Delay Time from IS_SCLK Falling Edge to IS_SDO	TSDOD			12	ns		17

CAD (KiCad official)

Symbol: ISD3900FYI
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: isd3900fyi-etched.step / isd3900fyi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isd3900fyi.step / isd3900fyi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (22 pp, sha256 55ea4d404bcec4e0, retrieved 2026-10-28, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF