# IS62WVS2568FBLL-20NLI

**ISSI(Integrated Silicon Solution)** · Pre-ordered Chips · SOIC-8

IS62WVS2568FBLL-20NLI from ISSI(Integrated Silicon Solution), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select, active low; a high level deselects the device and forces Standby mode, and SO goes high-impedance. |
| 2 | SO/SIO1 | bidirectional | Serial data output in SPI mode (shifted out after falling SCK edge, high-Z when deselected) and SIO1 in SDI/SQI mode. |
| 3 | DNU/SIO2 | bidirectional | Do Not Use in SPI and SDI modes; SIO2 in SQI mode. |
| 4 | VSS | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in SPI mode (instructions, addresses, data latched on rising SCK edge) and SIO0 in SDI/SQI mode. |
| 6 | SCK | input | Serial clock; input is latched on the rising edge and SO is updated after the falling edge. |
| 7 | HOLD#/SIO3 | bidirectional | Hold input in SPI/SDI mode (pulled low to pause communication, must be held high when unused) and SIO3 in SQI mode, where hold is unavailable. |
| 8 | VDD | power_in | Power supply, 2.2V to 3.6V for the IS62WVS2568FBLL. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ISSI(Integrated Silicon Solution) |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output HIGH Voltage | VOH | 2 |  |  | V | 2.2 ≤ VDD < 2.7, IOH = -0.1 mA | 17 |
| Output HIGH Voltage | VOH | 2.4 |  |  | V | 2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA | 17 |
| Output LOW Voltage | VOL |  |  | 0.4 | V | 2.2 ≤ VDD < 2.7, IOL = 0.1 mA | 17 |
| Input HIGH Voltage | VIH | 1.8 |  |  | V | 2.2 ≤ VDD < 2.7 (max VDD + 0.3) | 17 |
| Input HIGH Voltage | VIH | 2.2 |  |  | V | 2.7 ≤ VDD ≤ 3.6 (max VDD + 0.3) | 17 |
| Input LOW Voltage | VIL | -0.3 |  | 0.6 | V | 2.2 ≤ VDD < 2.7 | 17 |
| Input LOW Voltage | VIL | -0.3 |  | 0.8 | V | 2.7 ≤ VDD ≤ 3.6 | 17 |
| Data Retention Voltage | VDR |  | 1 |  | V |  | 17 |
| Input Leakage | ILI | -1 |  | 1 | µA | GND < VIN < VDD | 17 |
| Output Leakage | ILO | -1 |  | 1 | µA | GND < VIN < VDD, Output Disabled | 17 |
| VDD Dynamic Operating Supply Current | ICC |  |  | 8 | mA | VDD = Max, f = fMAX, CS# = VIL, IOUT = 0 mA, Ind., -20 | 18 |
| CMOS Standby Current (CMOS Inputs) | ISB2 |  | 4 | 20 | µA | VDD = Max, f = 0, CS# ≥ VDD - 0.2V, VIN ≤ 0.2V or VIN ≥ VDD - 0.2V, Ind., -20 | 18 |
| Clock Frequency | FCLK |  |  | 20 | MHz | -20 | 19 |
| CS# Setup Time | tCSS | 25 |  |  | ns | -20 | 19 |
| CS# Hold Time | tCSH | 50 |  |  | ns | -20 | 19 |
| CS# Disable Time | tCSD | 25 |  |  | ns | -20 | 19 |
| Data Setup Time | tDS | 10 |  |  | ns | -20 | 19 |
| Data Hold Time | tDH | 10 |  |  | ns | -20 | 19 |
| Clock High Time | tCKH | 23 |  |  | ns | -20 | 19 |
| Clock Low Time | tCKL | 23 |  |  | ns | -20 | 19 |
| Clock Delay Time | tCLD | 25 |  |  | ns | -20 | 19 |
| Output Valid from Clock Low | tV |  |  | 25 | ns | -20 | 19 |
| Output Hold Time | tOH | 0 |  |  | ns | -20 | 19 |
| CS# High to Output High-Z | tCHZ |  |  | 20 | ns | -20 | 19 |
| HOLD# Setup Time | tHS | 10 |  |  | ns | -20 | 19 |
| HOLD# Hold Time | tHH | 10 |  |  | ns | -20 | 19 |
| HOLD# Low to Output High-Z | tHZ |  |  | 20 | ns | -20 | 19 |
| HOLD# High to Output Valid | tHV |  |  | 50 | ns | -20 | 19 |
| Input capacitance (CS#, SCK) | CIN |  |  | 6 | pF | TA = 25°C, f = 1 MHz, VDD = VDD(typ) | 15 |
| Input/Output capacitance (other pins) | CI/O |  |  | 8 | pF | TA = 25°C, f = 1 MHz, VDD = VDD(typ) | 15 |
| Terminal Voltage with Respect to GND | Vterm | -0.2 |  | 3.9 | V | printed as -0.2 to +3.9 (VDD+0.3V) | 15 |
| Temperature Under Bias | tBIAS | -55 |  | 125 | C |  | 15 |
| VDD Related to GND | VDD | -0.2 |  | 3.9 | V | printed as -0.2 to +3.9 (VDD+0.3V) | 15 |
| Storage Temperature | tStg | -65 |  | 150 | C |  | 15 |
| Supply Voltage | VDD | 2.2 |  | 3.6 | V | Industrial operating range, IS62WVS2568FBLL | 15 |
| Ambient Temperature |  | -40 |  | 85 | C | Industrial | 15 |

## CAD (KiCad official)

- Symbol: `IS62WVS2568FBLL-20NLI`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `is62wvs2568fbll-20nli-etched.step` / `is62wvs2568fbll-20nli-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `is62wvs2568fbll-20nli.step` / `is62wvs2568fbll-20nli.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ISSI(Integrated Silicon Solution) datasheet](docs/is62wvs2568fbll-20nli-datasheet.pdf) (25 pp, sha256 `8d1ea53121e82159`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/is62wvs2568fbll-20nli-datasheet.pdf)