# IS31FL3729-QFLS4-TR

**ISSI Integrated Silicon Solution** · LED Drivers · QFN-32-EP(4x4)

IS31FL3729-QFLS4-TR from ISSI Integrated Silicon Solution, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS4 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 2 | CS5 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 3 | CS6 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 4 | CS7 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 5 | CS8 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 6 | CS9 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 7 | CS10 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 8 | CS11 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 9 | GND | power_in | Ground; must be connected to the thermal pad and system ground. |
| 10 | CS12 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 11 | CS13 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 12 | CS14 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 13 | CS15 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 14 | SW9/CS16 | power_out | Switch power source SW9 for the matrix row, also functioning as current sink CS16; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 15 | SW8 | power_out | Switch power source for matrix row 8; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 16 | SW7 | power_out | Switch power source for matrix row 7; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 17 | SW6 | power_out | Switch power source for matrix row 6; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 18 | SW5 | power_out | Switch power source for matrix row 5; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 19 | SW4 | power_out | Switch power source for matrix row 4; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 20 | SW3 | power_out | Switch power source for matrix row 3; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 21 | SW2 | power_out | Switch power source for matrix row 2; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 22 | SW1 | power_out | Switch power source for matrix row 1; SWx carries the combined current of the CSy pins, so its trace must be much wider than a CSy trace. |
| 23 | VCC | power_in | Power supply, 2.7 V to 5.5 V; place VCC capacitors close to this pin. |
| 24 | GND | power_in | Ground; must be connected to the thermal pad and system ground. |
| 25 | ISET | passive | Current setting pin; an external resistor RISET to GND sets the output current (example RISET=10kΩ), and it should be placed close to the chip. |
| 26 | SDA | bidirectional | I2C serial data, open-collector with pull-up resistor (about 4.7kΩ at 400kHz, 2kΩ at 1MHz); logic 0 max 0.4 V or 0.6 V depending on LGC. |
| 27 | SCL | input | I2C serial clock input, supporting up to 1MHz; logic-high threshold is 1.4 V or 2.4 V depending on LGC. |
| 28 | AD | input | I2C address setting; tie to GND, SCL, SDA or VCC to select A2:A1 of the 7-bit slave address. |
| 29 | SDB | input | Shutdown pin; pulling low places the chip in hardware shutdown, and a rising edge after VCC is above 2.4 V resets the I2C interface. |
| 30 | CS1 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 31 | CS2 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 32 | CS3 | output | Current sink output for the LED matrix; maximum constant current is 35 mA per CSy at RISET=10kΩ. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ISSI Integrated Silicon Solution |
| Package | QFN-32-EP(4x4) |
| Category | LED Drivers |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2.7 |  | 5.5 | V |  | 6 |
| Maximum constant current of CSx | IOUT |  |  | 35 | mA | RISET=10kΩ, GCC=100 0000, SL=0xFF | 6 |
| Quiescent power supply current | ICC |  | 2 | 3 | mA | VSDB=VCC, all LEDs off | 6 |
| Shutdown current | ISD |  | 3 | 5 | µA | VSDB=0V | 6 |
| Current switch headroom voltage SWx | VHR |  | 500 | 550 | mV | ISWITCH=600mA, RISET=10kΩ, GCC=100 0000, SL=0xFF | 6 |
| Current sink headroom voltage CSx | VHR |  | 400 | 500 | mV | ISINK=34mA, RISET=10kΩ, GCC=100 0000, SL=0xFF | 6 |
| Logic 0 input voltage (LGC=0) | VIL |  |  | 0.4 | V | VCC=2.7V~5.5V, LGC=0 | 6 |
| Logic 1 input voltage (LGC=0) | VIH | 1.4 |  |  | V | VCC=2.7V~5.5V, LGC=0 | 6 |
| Logic 0 input voltage (LGC=1) | VIL |  |  | 0.6 | V | VCC=2.7V~5.5V, LGC=1 | 6 |
| Logic 1 input voltage (LGC=1) | VIH | 2.4 |  |  | V | VCC=2.7V~5.5V, LGC=1 | 6 |
| Logic 0 input current | IIL |  |  | 5 | nA | SDB=L, VINPUT=L (Note 5) | 6 |
| Logic 1 input current | IIH |  |  | 5 | nA | SDB=L, VINPUT=H (Note 5) | 6 |
| Serial-clock frequency (Fast Mode) | fSCL |  |  | 400 | kHz |  | 7 |
| Serial-clock frequency (Fast Mode Plus) | fSCL |  |  | 1000 | kHz |  | 7 |
| Bus free time between STOP and START (Fast Mode) | tBUF | 1.3 |  |  | µs |  | 7 |
| Bus free time between STOP and START (Fast Mode Plus) | tBUF | 0.5 |  |  | µs |  | 7 |
| Hold time (repeated) START condition (Fast Mode) | tHD, STA | 0.6 |  |  | µs |  | 7 |
| Hold time (repeated) START condition (Fast Mode Plus) | tHD, STA | 0.26 |  |  | µs |  | 7 |
| Repeated START condition setup time (Fast Mode) | tSU, STA | 0.6 |  |  | µs |  | 7 |
| Repeated START condition setup time (Fast Mode Plus) | tSU, STA | 0.26 |  |  | µs |  | 7 |
| STOP condition setup time (Fast Mode) | tSU, STO | 0.6 |  |  | µs |  | 7 |
| STOP condition setup time (Fast Mode Plus) | tSU, STO | 0.26 |  |  | µs |  | 7 |
| Data setup time (Fast Mode) | tSU, DAT | 100 |  |  | ns |  | 7 |
| Data setup time (Fast Mode Plus) | tSU, DAT | 50 |  |  | ns |  | 7 |
| SCL clock low period (Fast Mode) | tLOW | 1.3 |  |  | µs |  | 7 |
| SCL clock low period (Fast Mode Plus) | tLOW | 0.5 |  |  | µs |  | 7 |
| SCL clock high period (Fast Mode) | tHIGH | 0.7 |  |  | µs |  | 7 |
| SCL clock high period (Fast Mode Plus) | tHIGH | 0.26 |  |  | µs |  | 7 |
| Rise time of SDA and SCL, receiving (Fast Mode) | tR |  |  | 300 | ns | receiving | 7 |
| Rise time of SDA and SCL, receiving (Fast Mode Plus) | tR |  |  | 120 | ns | receiving | 7 |
| Fall time of SDA and SCL, receiving (Fast Mode) | tF |  |  | 300 | ns | receiving | 7 |
| Fall time of SDA and SCL, receiving (Fast Mode Plus) | tF |  |  | 120 | ns | receiving | 7 |
| Supply voltage (absolute maximum) | VCC | -0.3 |  | 6 | V |  | 6 |
| Voltage at any input pin (absolute maximum) |  | -0.3 |  |  | V |  | 6 |
| Maximum junction temperature | TJMAX |  |  | 150 | °C |  | 6 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 6 |
| Operating temperature range | TA=TJ | -40 |  | 125 | °C |  | 6 |
| ESD (HBM) |  | -8 |  | 8 | kV |  | 6 |
| ESD (CDM) |  | -750 |  | 750 | V |  | 6 |
| Input Schmitt trigger hysteresis | VHYS |  | 0.2 |  | V | VCC=3.6V, LGC=0, LGC=1 | 6 |
| Average current on each LED | ILED |  | 4.22 |  | mA | RISET=10kΩ, GCC=100 0000, SL=0xFF, n=8, Duty=1/8.29 | 6 |
| Period of scanning | tSCAN |  | 30 |  | µs | B2h=0x01 (PWM frequency = 32kHz) | 6 |
| Non-overlap blanking time during scan | tNOL1 |  | 0.8 |  | µs | B2h=0x01 (PWM frequency = 32kHz) | 6 |
| Delay total time for CS1 to CS16 | tNOL2 |  | 0.27 |  | µs | B2h=0x01 (PWM frequency = 32kHz) | 6 |
| Package thermal resistance, junction to ambient (QFN) | θJA |  | 52.2 |  | °C/W | 4-layer standard test PCB based on JESD 51-2A | 6 |

## CAD (KiCad official)

- Symbol: `IS31FL3729-QFLS4-TR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm`
- 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `is31fl3729-qfls4-tr-etched.step` / `is31fl3729-qfls4-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `is31fl3729-qfls4-tr.step` / `is31fl3729-qfls4-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ISSI Integrated Silicon Solution datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836133233156096) (24 pp, sha256 `afd9a2c45d575a8c`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/is31fl3729-qfls4-tr-datasheet.pdf)