IS25WP128F-JBLE-TR

{
  "slug": "is25wp128f-jble-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "ISSI Integrated Silicon Solution NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "memory",
    "is25wp128f-jble-tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "is25wp128f-jble-tr.kicad_sym",
    "is25wp128f-jble-tr.kicad_mod",
    "is25wp128f-jble-tr.glb",
    "is25wp128f-jble-tr.step",
    "is25wp128f-jble-tr.lbr",
    "docs/hero.png",
    "docs/is25wp128f-jble-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "is25wp128f-jble-tr-hero.glb",
    "is25wp128f-jble-tr-hero.overlay.json",
    "is25wp128f-jble-tr-etched.glb"
  ],
  "component": {
    "mpn": "IS25WP128F-JBLE-TR",
    "manufacturer": "ISSI Integrated Silicon Solution",
    "package": "SOIC-8-208mil",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "NOR FLASH",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589832110325600256",
    "parts": {
      "symbol": "is25wp128f-jble-tr.kicad_sym",
      "footprint": "is25wp128f-jble-tr.kicad_mod",
      "model_3d": "is25wp128f-jble-tr-hero.glb",
      "model_3d_plain": "is25wp128f-jble-tr-etched.glb",
      "model_3d_step": "is25wp128f-jble-tr-etched.step",
      "model_3d_step_plain": "is25wp128f-jble-tr.step",
      "lbr": "is25wp128f-jble-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2062868"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T20:08:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CE#",
        "type": "input",
        "description": "Chip Enable: driving CE# high deselects the device and puts the outputs in high impedance, while driving it low selects the device, and after power-up CE# must go high-to-low before an instruction is accepted."
      },
      {
        "number": "2",
        "name": "SO (IO1)",
        "type": "bidirectional",
        "description": "Serial Data Output (SO, IO1) is read on the falling edge of SCK in standard SPI and becomes the bidirectional IO1 in Dual and Quad SPI modes."
      },
      {
        "number": "3",
        "name": "WP# (IO2)",
        "type": "bidirectional",
        "description": "Write Protect/Serial Data IO2: with SRWD set to 1, pulling WP# low write-protects the Status Register bits, and this pin becomes IO2 when the QE bit is set to 1, so WP# is then unavailable."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground: connect to ground when referenced to Vcc."
      },
      {
        "number": "5",
        "name": "SI (IO0)",
        "type": "bidirectional",
        "description": "Serial Data Input (SI, IO0) writes instructions, addresses or data on the rising edge of SCK in standard SPI and becomes the bidirectional IO0 in Dual and Quad SPI modes."
      },
      {
        "number": "6",
        "name": "SCK",
        "type": "input",
        "description": "Serial Data Clock: synchronizes the input and output timing operations of the device."
      },
      {
        "number": "7",
        "name": "HOLD# or RESET# (IO3)",
        "type": "bidirectional",
        "description": "HOLD# pauses serial communication while active low with CE# low (SO goes high impedance) and is the default function, or it can be set to RESET# via the P7 bit of the Read Register; when QE=1 it becomes IO3."
      },
      {
        "number": "8",
        "name": "Vcc",
        "type": "power_in",
        "description": "Power: device core power supply; for the IS25WP128F the supply range is 1.65V to 1.95V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Ordering code IS25WP128F-JBLE-TR decodes as J (standard option), B (8-pin SOIC 208mil), L (RoHS), E ; Pin 7 defaults to HOLD# (IO3) and can be reconfigured to RESET# by the P7 bit of the Read Register; ",
          "1/8 pins cited to the wrong page (name found elsewhere): ['6:SCK@p10']"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0755,
        "at": "2026-10-17T20:05:51"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589832110325600256",
        "pages": 180,
        "sha256": "8eee02b03531933f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "is25wp128f-jble-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "is25wp128f-jble-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "028fed8b830d2a694b7678bf9a68022b77b522c44244f7b00c167b2b7fabc83a",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}