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Ray Publish 0.1.0 e7d2d96 4d ago

IS25WP128F-JBLE-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8-208mil

IS25WP128F-JBLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: driving CE# high deselects the device and puts the outputs in high impedance, while driving it low selects the device, and after power-up CE# must go high-to-low before an instruction is accepted.
2 SO (IO1) bidirectional Serial Data Output (SO, IO1) is read on the falling edge of SCK in standard SPI and becomes the bidirectional IO1 in Dual and Quad SPI modes.
3 WP# (IO2) bidirectional Write Protect/Serial Data IO2: with SRWD set to 1, pulling WP# low write-protects the Status Register bits, and this pin becomes IO2 when the QE bit is set to 1, so WP# is then unavailable.
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional Serial Data Input (SI, IO0) writes instructions, addresses or data on the rising edge of SCK in standard SPI and becomes the bidirectional IO0 in Dual and Quad SPI modes.
6 SCK input Serial Data Clock: synchronizes the input and output timing operations of the device.
7 HOLD# or RESET# (IO3) bidirectional HOLD# pauses serial communication while active low with CE# low (SO goes high impedance) and is the default function, or it can be set to RESET# via the P7 bit of the Read Register; when QE=1 it becomes IO3.
8 Vcc power_in Power: device core power supply; for the IS25WP128F the supply range is 1.65V to 1.95V.

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOIC-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage with Respect to Ground on All Pins -0.5 V 163
All Output Voltage with Respect to Ground -0.5 V 163
Storage Temperature -65 150 °C 163
Surface Mount Lead Soldering Temperature 260 °C Lead-free package, 3 seconds 163
VCC supply voltage (IS25WP) VCC -0.5 2.5 V IS25WP 163
Operating Temperature -40 105 °C Extended Grade E 163
VCC Power Supply (IS25WP) VCC 1.65 1.8 1.95 V IS25WP 163
VCC Active Read current NORD ICC1 8 9 mA NORD at 80MHz 164
VCC Active Read current FRD Single ICC1 9 11 mA FRD Single at 166MHz 164
VCC Active Read current FRD Dual ICC1 11 12 mA FRD Dual at 166MHz 164
VCC Active Read current FRD Quad ICC1 14 15 mA FRD Quad at 166MHz 164
VCC Active Read current FRD Single ICC1 9 10.5 mA FRD Single at 133MHz 164
VCC Active Read current FRD Dual ICC1 10 11 mA FRD Dual at 133MHz 164
VCC Active Read current FRD Quad ICC1 12.5 13.5 mA FRD Quad at 133MHz 164
VCC Active Read current FRD Quad ICC1 10 11 mA FRD Quad at 83MHz 164
VCC Active Read current FRD Quad ICC1 11 12 mA FRD Quad at 104MHz 164
VCC Active Read current FRD Single DTR ICC1 8.5 9.5 mA FRD Single DTR at 80MHz 164
VCC Active Read current FRD Dual DTR ICC1 10 11 mA FRD Dual DTR at 80MHz 164
VCC Active Read current FRD Quad DTR ICC1 11 12 mA FRD Quad DTR at 80MHz 164
VCC Program Current ICC2 30 mA CE# = VCC, 105°C 164
VCC WRSR Current ICC3 30 mA CE# = VCC, 105°C 164
VCC Erase Current (SER/4SER/BER32/4BER32/BER64/4BER64) ICC4 30 mA CE# = VCC, 105°C 164
VCC Erase Current (CE) ICC5 30 mA CE# = VCC, 105°C 164
VCC Standby Current CMOS (IS25WP) ISB1 45 µA CE# = VCC, VIN = GND or VCC, IS25WP, 105°C 164
Deep power down current (IS25WP) ISB2 15 µA CE# = VCC, VIN = GND or VCC, IS25WP, 105°C 164
Input Leakage Current ILI -1 1 µA VIN = 0V to VCC 164
Output Leakage Current ILO -1 1 µA VIN = 0V to VCC 164
Input Low Voltage VIL -0.5 V 164
Output Low Voltage VOL 0.2 V IOL = 100 µA 164
Clock Frequency fCT (IS25WP) fCT 0 166 MHz VCC = 1.7V to 1.95V 166
Clock Frequency fCT (IS25WP) fCT 0 133 MHz VCC = 1.65V to 1.95V 166
Clock Frequency for fast read DTR fCT 0 80 MHz SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, QPI DTR 166
Clock Frequency for read (03h) fC 0 80 MHz 166
SCK Rise Time (peak to peak) tCLCH 0.1 V/ns 166
SCK Fall Time (peak to peak) tCHCL 0.1 V/ns 166
CE# High Time for read mode tCEH 7 ns For read mode 166
CE# High Time for write mode tCEH 20 ns For write mode 166
CE# Setup Time tCS 3 ns 166
CE# Hold Time tCH 3 ns 166
CE# Not Active Hold Time tCHSL 3 ns 166
CE# Not Active Setup Time tSHCH 3 ns 166
Data In Setup Time STR tDS 2 ns STR 166
Data In Setup Time DTR tDS 1.5 ns DTR 166
Data In Hold Time STR tDH 2 ns STR 166
Data In Hold Time DTR tDH 1.5 ns DTR 166
Output Valid (IS25WP) tV 5.5 ns 1.65~1.95V, -40°C to 125°C, @10pF 166
Output Valid (IS25WP) tV 7 ns 1.65~1.95V, -40°C to 125°C, @30pF 166
Output Hold Time tOH 2 ns 166
Output Disable Time tDIS 8 ns 166
Write Protect Setup Time tWHSL 20 ns 166
Write Protect Hold Time tSHWL 100 ns 166
Sector Erase Time (4Kbyte) tEC 100 300 ms 167
Block Erase Time (64Kbyte) tEC 0.17 1 s 167
Chip Erase Time tEC 35 90 s 167
Page Program Time tPP 0.2 0.8 ms 167
Write Status Register time tW 2 15 ms 167
Vcc(min) to CE# Low (power-up) tVCE 300 µs 170
Endurance 100000 Cycles JEDEC Standard A117 171
Input Capacitance (CE#, SCK) CIN 6 pF VIN = 0V, TA = 25°C, VCC = 1.8V, 1MHz 165
Input/Output Capacitance (other pins) CIN/OUT 10 pF VIN/OUT = 0V, TA = 25°C, VCC = 1.8V, 1MHz 165

CAD (KiCad official)

  • Symbol: IS25WP128F-JBLE-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
  • 3D model files: is25wp128f-jble-tr-etched.step / is25wp128f-jble-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25wp128f-jble-tr.step / is25wp128f-jble-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (180 pp, sha256 8eee02b03531933f, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF