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IS25LP512M-JLLE
Public Made by Adomby adom
ISSI(Integrated Silicon Solution) Pre-ordered Chips, WSON-8-EP(6x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIS25LP512M-JLLE
ISSI(Integrated Silicon Solution) · Pre-ordered Chips · WSON-8-EP(6x8)
IS25LP512M-JLLE from ISSI(Integrated Silicon Solution), in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable: when high the device is deselected, outputs are high impedance and it enters low-power standby; it must transition high to low after power-up before a new instruction is accepted. |
| 2 | SO (IO1) | bidirectional | Serial Data Output in standard SPI (data shifted out on the falling edge of SCK) and bidirectional IO1 in Dual and Quad modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect pin that protects the Status Register bits (SRWD, QE, BP3-BP0) when SRWD=1 and WP# is low, and serves as IO2 in Quad mode, where the WP# function is unavailable when QE=1. |
| 4 | GND | power_in | Ground reference for the device supply. |
| 5 | SI (IO0) | bidirectional | Serial Data Input in standard SPI (sampled on the rising edge of SCK) and bidirectional IO0 in Dual and Quad modes. |
| 6 | SCK | input | Serial Data Clock that synchronizes input and output timing operations. |
| 7 | HOLD# or RESET# (IO3) | bidirectional | HOLD# (default, P7=0) or RESET# (P7=1) when QE=0, with no dedicated RESET# on the WSON, and IO3 in Quad mode when QE=1; HOLD# is active low and pauses serial communication while the device is selected. |
| 8 | VCC | power_in | Device core power supply, 2.30V to 3.60V for IS25LP512M. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI(Integrated Silicon Solution) |
| Package | WSON-8-EP(6x8) |
| Category | Interface ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (IS25LP) | VCC | 2.3 | 3 | 3.6 | V | Operating range | 170 |
| Ambient operating temperature (Extended grade E) | -40 | 105 | °C | Extended Grade E | 170 | ||
| Supply voltage absolute maximum (IS25LP) | VCC | -0.5 | 6 | V | IS25LP | 170 | |
| Storage temperature | -65 | 150 | °C | 170 | |||
| Lead soldering temperature (lead-free) | 260 | °C | Lead-free package, 3 seconds | 170 | |||
| Input/output voltage minimum | -0.5 | V | With respect to ground on all pins; max printed as VCC + 0.5V | 170 | |||
| VCC active read current | ICC1 | 13 | 16 | mA | NORD | 171 | |
| VCC active read current | ICC1 | 16 | 20 | mA | FRD Single at 133MHz | 171 | |
| VCC active read current | ICC1 | 18 | 22 | mA | FRD Dual at 133MHz | 171 | |
| VCC active read current | ICC1 | 22 | 27 | mA | FRD Quad at 133MHz | 171 | |
| VCC program current | ICC2 | 30 | 35 | mA | CE# = VCC, 85°C | 171 | |
| VCC program current | ICC2 | 35 | mA | CE# = VCC, 105°C | 171 | ||
| VCC WRSR current | ICC3 | 60 | 80 | mA | CE# = VCC, 85°C | 171 | |
| VCC WRSR current | ICC3 | 80 | mA | CE# = VCC, 105°C | 171 | ||
| VCC erase current (sector/block) | ICC4 | 30 | 35 | mA | CE# = VCC, 85°C | 171 | |
| VCC erase current (chip) | ICC5 | 60 | 80 | mA | CE# = VCC, 85°C | 171 | |
| VCC standby current CMOS (IS25LP) | ISB1 | 21 | 90 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 171 | |
| VCC standby current CMOS (IS25LP) | ISB1 | 140 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 171 | ||
| Deep power down current (IS25LP) | ISB2 | 17 | 35 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 171 | |
| Deep power down current (IS25LP) | ISB2 | 50 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 171 | ||
| Input leakage current | ILI | -2 | 2 | µA | VIN = 0V to VCC | 171 | |
| Output leakage current | ILO | -2 | 2 | µA | VIN = 0V to VCC | 171 | |
| Input low voltage (min only; max printed as 0.3VCC) | VIL | -0.5 | V | 171 | |||
| Output low voltage | VOL | 0.2 | V | IOL = 100 µA | 171 | ||
| Input capacitance (CE#, SCK) | CIN | 12 | pF | VIN = 0V, TA = 25°C, VCC=3V, 1MHz, IS25LP | 172 | ||
| Input/output capacitance (other pins) | CIN/OUT | 16 | pF | VIN/OUT = 0V, TA = 25°C, VCC=3V, 1MHz, IS25LP | 172 | ||
| Clock frequency (IS25LP) | fCT | 0 | 133 | MHz | Except fast read DTR and read (03h) | 173 | |
| Clock frequency for fast read DTR | fCT | 0 | 66 | MHz | SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR | 173 | |
| Clock frequency for read (03h) | fC | 0 | 50 | MHz | 173 | ||
| CE# high time | tCEH | 7 | ns | 173 | |||
| CE# setup time | tCS | 5 | ns | 173 | |||
| CE# hold time | tCH | 3 | ns | 173 | |||
| Data in setup time | tDS | 2 | ns | STR | 173 | ||
| Data in hold time | tDH | 2 | ns | STR | 173 | ||
| Output valid (IS25LP) | tV | 7 | ns | 2.3~3.6V, -40°C to 125°C, @ CL = 10pF | 173 | ||
| Output valid (IS25LP) | tV | 8.5 | ns | 2.3~3.6V, -40°C to 125°C, @ CL = 30pF | 173 | ||
| Output hold time | tOH | 1 | ns | 173 | |||
| Output disable time | tDIS | 8 | ns | 173 | |||
| Sector erase time (4Kbyte) | tEC | 100 | 300 | ms | 174 | ||
| Chip erase time | tEC | 80 | 270 | s | 174 | ||
| Page program time (256byte) | tPP | 0.3 | 1 | ms | 174 | ||
| Release deep power down (IS25LP) | tRES1 | 3 | µs | IS25LP | 174 | ||
| Write status register time | tW | 2 | 15 | ms | 174 | ||
| Vcc(min) to CE# low | tVCE | 300 | us | 177 | |||
| Write inhibit voltage (IS25LP) | VWI | 2.1 | V | IS25LP | 177 | ||
| Endurance | 100000 | Cycles | JEDEC Standard A117 | 178 | |||
| Data retention | 20 | Years | JEDEC Standard A117 | 178 | |||
| Latch-up | -100 | 100 | mA | JEDEC Standard 78 | 178 |
CAD (KiCad official)
- Symbol:
IS25LP512M-JLLE - Footprint:
Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm - 3D model: WSON-8-EP(6x8), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
is25lp512m-jlle-etched.step/is25lp512m-jlle-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);is25lp512m-jlle.step/is25lp512m-jlle.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ISSI(Integrated Silicon Solution) datasheet (185 pp, sha256
6a953943df144920, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).