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IS25LP128F-JBLE-TR

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ISSI Integrated Silicon Solution NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IS25LP128F-JBLE-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8-208mil

IS25LP128F-JBLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable (CE#) enables and disables the device; when CE# is high the device is deselected and the outputs are high impedance, and after power-up CE# must go from high to low before a new instruction is accepted.
2 SO (IO1) bidirectional In standard SPI, SO is the unidirectional serial data output read on the falling edge of SCK; in Dual and Quad SPI it becomes the bidirectional IO1 pin.
3 WP# (IO2) bidirectional With SRWD set to 1 and WP# pulled low, the Status Register bits (SRWD, QE, BP3-BP0) are write-protected; when QE is set to 1 the pin is used as IO2 and the WP# function is unavailable.
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional In standard SPI, SI is the unidirectional serial data input sampled on the rising edge of SCK; in Dual and Quad SPI it becomes the bidirectional IO0 pin.
6 SCK input Serial Data Clock provides the synchronized clock for input and output timing operations.
7 HOLD# or RESET# (IO3) bidirectional With QE=0 the pin acts as HOLD# (default, P7=0, pauses serial communication while CE# is low and puts SO in high impedance) or as RESET# when P7=1 in the Read Register; when QE=1 it becomes IO3.
8 Vcc power_in Device core power supply.

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOIC-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 163
Surface Mount Lead Soldering Temperature (Lead-free Package) 260 °C 3 Seconds 163
Input Voltage with Respect to Ground on All Pins (lower limit) -0.5 V Printed upper limit is VCC + 0.5V 163
All Output Voltage with Respect to Ground (lower limit) -0.5 V Printed upper limit is VCC + 0.5V 163
VCC Supply Voltage absolute maximum (IS25LP) VCC -0.5 6 V IS25LP 163
Operating Temperature, Extended Grade E -40 105 °C Extended Grade E 163
VCC Power Supply (IS25LP) VCC 2.3 3 3.6 V IS25LP 163
VCC Active Read current ICC1 8 9 mA NORD at 80MHz 164
VCC Active Read current ICC1 9 11 mA FRD Single at 166MHz 164
VCC Active Read current ICC1 11 12 mA FRD Dual at 166MHz 164
VCC Active Read current ICC1 14 15 mA FRD Quad at 166MHz 164
VCC Active Read current ICC1 9 10.5 mA FRD Single at 133MHz 164
VCC Active Read current ICC1 10 11 mA FRD Dual at 133MHz 164
VCC Active Read current ICC1 12.5 13.5 mA FRD Quad at 133MHz 164
VCC Active Read current ICC1 8.5 9.5 mA FRD Single DTR at 80MHz 164
VCC Program Current ICC2 25 30 mA CE# = VCC, 85°C 164
VCC Program Current ICC2 30 mA CE# = VCC, 105°C 164
VCC WRSR Current ICC3 25 30 mA CE# = VCC, 85°C 164
VCC WRSR Current ICC3 30 mA CE# = VCC, 105°C 164
VCC Erase Current (SER/4SER/BER32/4BER32/BER64/4BER64) ICC4 25 30 mA CE# = VCC, 85°C 164
VCC Erase Current (SER/4SER/BER32/4BER32/BER64/4BER64) ICC4 30 mA CE# = VCC, 105°C 164
VCC Erase Current (CE) ICC5 25 30 mA CE# = VCC, 85°C 164
VCC Erase Current (CE) ICC5 30 mA CE# = VCC, 105°C 164
VCC Standby Current CMOS (IS25LP) ISB1 8 30 µA CE# = VCC, VIN = GND or VCC, 85°C 164
VCC Standby Current CMOS (IS25LP) ISB1 45 µA CE# = VCC, VIN = GND or VCC, 105°C 164
Deep power down current (IS25LP) ISB2 5 15 µA CE# = VCC, VIN = GND or VCC, 85°C 164
Deep power down current (IS25LP) ISB2 20 µA CE# = VCC, VIN = GND or VCC, 105°C 164
Input Leakage Current ILI -1 1 µA VIN = 0V to VCC 164
Output Leakage Current ILO -1 1 µA VIN = 0V to VCC 164
Input Low Voltage VIL -0.5 V Printed upper limit is 0.3VCC 164
Output Low Voltage VOL 0.2 V IOL = 100 µA 164
Input Capacitance (CE#, SCK) CIN 6 pF VIN = 0V 165
Input/Output Capacitance (other pins) CIN/OUT 8 pF VIN/OUT = 0V 165
Input Rise and Fall Times TR,TF 5 ns 165
Clock Frequency except for fast read DTR and read (03h) fCT 0 166 MHz IS25LP, VCC = 2.7V to 3.6V 166
Clock Frequency except for fast read DTR and read (03h) fCT 0 133 MHz IS25LP, VCC = 2.3V to 3.6V 166
Clock Frequency for fast read DTR fCT 0 80 MHz SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR 166
Clock Frequency for read (03h) fC 0 80 MHz 166
SCK Rise Time (peak to peak) tCLCH 0.1 V/ns 166
SCK Fall Time (peak to peak) tCHCL 0.1 V/ns 166
CE# High Time tCEH 7 ns For read mode 166
CE# High Time tCEH 20 ns For write mode 166
Output Valid tV 5.5 ns 2.7~3.6V, -40°C to 85°C, @10pF 166
Output Valid tV 7 ns 2.7~3.6V, -40°C to 85°C, @30pF 166
Output Valid tV 6.5 ns 2.3~3.6V, -40°C to 125°C, @10pF 166
Output Valid tV 8 ns 2.3~3.6V, -40°C to 125°C, @30pF 166
Output Disable Time tDIS 8 ns 166
Data In Setup Time tDS 2 ns STR 166
Data In Setup Time tDS 1.5 ns DTR 166
Data in Hold Time tDH 2 ns STR 166
Data in Hold Time tDH 1.5 ns DTR 166
Sector Erase Time (4Kbyte) tEC 100 300 ms 167
Block Erase Time (32Kbyte) tEC 0.14 0.5 s 167
Block Erase time (64Kbyte) tEC 0.17 1 s 167
Chip Erase Time tEC 35 90 s 167
Page Program Time tPP 0.2 0.8 ms 167

CAD (KiCad official)

  • Symbol: IS25LP128F-JBLE-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
  • 3D model files: is25lp128f-jble-tr-etched.step / is25lp128f-jble-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp128f-jble-tr.step / is25lp128f-jble-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (180 pp, sha256 8eee02b03531933f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF