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IS25LP080D-JNLA3-TR

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ISSI(Integrated Silicon Solution) Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IS25LP080D-JNLA3-TR

ISSI(Integrated Silicon Solution) · Pre-ordered Chips · SOIC-8

IS25LP080D-JNLA3-TR from ISSI(Integrated Silicon Solution), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: when high the device is deselected, outputs are high-impedance and it enters low-power standby; a high-to-low transition is required after power-up before a new instruction is accepted.
2 SO (IO1) bidirectional Serial Data Output in standard SPI (data read on the falling edge of SCK), becoming bidirectional IO1 in Dual and Quad SPI and QPI modes.
3 WP# (IO2) bidirectional Write Protect protects the Status Register bits (SRWD, QE, BP3-BP0) when SRWD=1 and WP# is low; becomes IO2 and the WP# function is unavailable when QE=1.
4 GND power_in Ground reference for Vcc.
5 SI (IO0) bidirectional Serial Data Input for instructions, addresses and data on the rising edge of SCK, becoming bidirectional IO0 in Dual and Quad SPI and QPI modes.
6 SCK input Serial Data Clock providing synchronized timing for input and output operations.
7 HOLD# or RESET# (IO3) bidirectional HOLD# (P7=0 default) pauses serial communication while selected, or RESET# (P7=1) is a hardware reset (active low, output High-Z); becomes IO3 and HOLD#/RESET# is unavailable when QE=1.
8 Vcc power_in Device core power supply, 2.30V to 3.60V for IS25LP.

Key specifications

Parameter Value
Manufacturer ISSI(Integrated Silicon Solution)
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 96
Input Voltage on All Pins (min only) -0.5 V with respect to ground; max is VCC + 0.5V 96
Supply Voltage VCC (IS25LP) VCC -0.5 6 V IS25LP 96
ESD Voltage (HBM) -2000 2000 V ANSI/ESDA/JEDEC JS-001 96
Operating Temperature, Automotive Grade A3 -40 125 °C A3 96
VCC Power Supply (IS25LP) VCC 2.3 3 3.6 V IS25LP 96
VCC Active Read current ICC1 4 12 mA NORD at 50MHz 97
VCC Active Read current ICC1 6 14 mA FRD Single at 133MHz 97
VCC Active Read current ICC1 8 15 mA FRD Dual at 133MHz 97
VCC Active Read current ICC1 10 17 mA FRD Quad at 133MHz 97
VCC Active Read current ICC1 9 16 mA FRD Quad at 104MHz 97
VCC Program Current ICC2 22 25 mA CE# = VCC, 85°C 97
VCC Program Current ICC2 25 mA CE# = VCC, 125°C 97
VCC WRSR Current ICC3 22 25 mA CE# = VCC, 85°C 97
VCC WRSR Current ICC3 25 mA CE# = VCC, 125°C 97
VCC Erase Current (SER/BER32/BER64) ICC4 22 25 mA CE# = VCC, 85°C 97
VCC Erase Current (SER/BER32/BER64) ICC4 25 mA CE# = VCC, 125°C 97
VCC Erase Current (CE) ICC5 22 25 mA CE# = VCC, 85°C 97
VCC Erase Current (CE) ICC5 25 mA CE# = VCC, 125°C 97
VCC Standby Current CMOS ISB1 8 15 µA CE# = VCC, VIN = GND or VCC, 85°C 97
VCC Standby Current CMOS ISB1 30 µA CE# = VCC, VIN = GND or VCC, 125°C 97
Deep power down current (IS25LP) ISB2 6 10 µA CE# = VCC, VIN = GND or VCC, 85°C 97
Deep power down current (IS25LP) ISB2 20 µA CE# = VCC, VIN = GND or VCC, 125°C 97
Input Leakage Current ILI -1 1 µA VIN = 0V to VCC 97
Output Leakage Current ILO -1 1 µA VIN = 0V to VCC 97
Input Low Voltage (min only) VIL -0.5 V max is 0.3VCC 97
Output Low Voltage VOL 0.2 V IOL = 100 µA 97
Input Capacitance (CE#, SCK) CIN 6 pF VIN = 0V, TA = 25°C, VCC=3V, 1MHz 98
Input/Output Capacitance (other pins) CIN/OUT 8 pF VIN/OUT = 0V, TA = 25°C, VCC=3V, 1MHz 98
Clock Frequency for fast read fCT 0 133 MHz SPI, Dual, Dual I/O, Quad I/O, and QPI 99
Clock Frequency for fast read DTR fCT 0 66 MHz SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR 99
Clock Frequency for read (03h) fC 0 50 MHz 99
CE# High Time tCEH 7 ns 99
CE# Setup Time tCS 5 ns 99
CE# Hold Time tCH 5 ns 99
Data In Setup Time tDS 2 ns STR 99
Data in Hold Time tDH 2 ns STR 99
Output Valid tV 7 ns @ 133MHz (CL = 15pF) 99
Output Hold Time tOH 2 ns 99
Sector Erase Time (4Kbyte) tEC 70 300 ms 99
Block Erase Time (64Kbyte) tEC 0.15 1 s 99
Chip Erase Time 8Mb tEC 2 6 s 8Mb 99
Page Program Time tPP 0.2 0.8 ms 99
Write Status Register time tW 2 15 ms 100
Vcc(min) to CE# Low tVCE 300 µs 104
Endurance 100000 Cycles JEDEC Standard A117 105
Data Retention 20 Years JEDEC Standard A117 105
Latch-Up -100 100 mA JEDEC Standard 78 105

CAD (KiCad official)

  • Symbol: IS25LP080D-JNLA3-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: is25lp080d-jnla3-tr-etched.step / is25lp080d-jnla3-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp080d-jnla3-tr.step / is25lp080d-jnla3-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI(Integrated Silicon Solution) datasheet (113 pp, sha256 4ba38cc41a442352, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF