component
IS25LP064A-JLLE
Public Made by Adomby adom
ISSI(Integrated Silicon Solution) Pre-ordered Chips, WSON-8-EP(6x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IS25LP064A-JLLE
ISSI(Integrated Silicon Solution) · Pre-ordered Chips · WSON-8-EP(6x8)
IS25LP064A-JLLE from ISSI(Integrated Silicon Solution), in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable (CE#) selects the device when low and deselects it when high, with outputs in high impedance; after power-up CE# must transition from high to low before a new instruction is accepted. |
| 2 | SO (IO1) | bidirectional | Serial Data Output (SO/IO1) reads data or status on the falling edge of SCK in standard SPI and acts as bidirectional IO1 in Dual and Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect (WP#/IO2) write-protects the Status Register together with the SRWD bit when pulled low and becomes IO2 when QE is set to 1. |
| 4 | GND | power_in | Ground: connect to ground when referenced to Vcc. |
| 5 | SI (IO0) | bidirectional | Serial Data Input (SI/IO0) writes instructions, addresses or data on the rising edge of SCK in standard SPI and acts as bidirectional IO0 in Dual and Quad SPI modes. |
| 6 | SCK | input | Serial Data Clock (SCK) provides the synchronized clock for input and output timing operations. |
| 7 | HOLD# (IO3) | bidirectional | HOLD# (IO3) is active low and pauses serial communication without resetting the sequence when CE# is low, becoming IO3 when QE is set to 1; the pin defaults to HOLD# (RESET# only on the optional part). |
| 8 | Vcc | power_in | Power: device core power supply. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI(Integrated Silicon Solution) |
| Package | WSON-8-EP(6x8) |
| Category | Interface ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | -65 | 150 | °C | 82 | |||
| Surface Mount Lead Soldering Temperature - Standard Package | 240 | °C | 3 Seconds, standard package | 82 | |||
| Surface Mount Lead Soldering Temperature - Lead-free Package | 260 | °C | 3 Seconds, lead-free package | 82 | |||
| Input Voltage with Respect to Ground on All Pins | -0.5 | V | Max VCC + 0.5V | 82 | |||
| All Output Voltage with Respect to Ground | -0.5 | V | Max VCC + 0.5V | 82 | |||
| VCC Supply Voltage | VCC | -0.5 | 6 | V | 82 | ||
| Electrostatic Discharge Voltage (Human Body Model) | -2000 | 2000 | V | ANSI/ESDA/JEDEC JS-001 | 82 | ||
| Operating Temperature (Extended Grade E) | -40 | 105 | °C | 82 | |||
| VCC Power Supply (2.7V to 3.6V band) | VCC | 2.7 | 3 | 3.6 | V | Max. 133MHz | 82 |
| VCC Power Supply (2.3V to 3.6V band) | VCC | 2.3 | 3 | 3.6 | V | Max. 104MHz | 82 |
| VCC Active Read Current | ICC1 | 5 | 9 | mA | NORD at 50MHz | 83 | |
| VCC Active Read Current | ICC1 | 7 | 11 | mA | FRD Single at 133MHz | 83 | |
| VCC Active Read Current | ICC1 | 10 | 14 | mA | FRD Quad at 133MHz | 83 | |
| VCC Program Current | ICC2 | 17 | 25 | mA | CE# = VCC, 85°C | 83 | |
| VCC Program Current | ICC2 | 25 | mA | CE# = VCC, 105°C | 83 | ||
| VCC WRSR Current | ICC3 | 17 | 25 | mA | CE# = VCC, 85°C | 83 | |
| VCC WRSR Current | ICC3 | 25 | mA | CE# = VCC, 105°C | 83 | ||
| VCC Erase Current (SER/BER32K/BER64K) | ICC4 | 17 | 25 | mA | CE# = VCC, 85°C | 83 | |
| VCC Erase Current (SER/BER32K/BER64K) | ICC4 | 25 | mA | CE# = VCC, 105°C | 83 | ||
| VCC Erase Current (CE) | ICC5 | 17 | 25 | mA | CE# = VCC, 85°C | 83 | |
| VCC Erase Current (CE) | ICC5 | 25 | mA | CE# = VCC, 105°C | 83 | ||
| VCC Standby Current CMOS | ISB1 | 10 | 20 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 83 | |
| VCC Standby Current CMOS | ISB1 | 35 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 83 | ||
| VCC Standby Current CMOS | ISB1 | 60 | µA | CE# = VCC, VIN = GND or VCC, 125°C | 83 | ||
| Deep power down current | ISB2 | 5 | 10 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 83 | |
| Deep power down current | ISB2 | 20 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 83 | ||
| Deep power down current | ISB2 | 30 | µA | CE# = VCC, VIN = GND or VCC, 125°C | 83 | ||
| Input Leakage Current | ILI | -1 | 1 | µA | VIN = 0V to VCC | 83 | |
| Output Leakage Current | ILO | -1 | 1 | µA | VIN = 0V to VCC | 83 | |
| Input Low Voltage | VIL | -0.5 | V | Max 0.3VCC | 83 | ||
| Output Low Voltage | VOL | 0.2 | V | VMIN < VCC < VMAX, IOL = 100 µA | 83 | ||
| Input Capacitance (CE#, SCK) | CIN | 6 | pF | VIN = 0V | 84 | ||
| Input/Output Capacitance (other pins) | CIN/OUT | 8 | pF | VIN/OUT = 0V | 84 | ||
| Clock Frequency except for fast read DTR and read (03h), Vcc=2.7V~3.6V | fCT | 0 | 133 | MHz | Vcc=2.7V~3.6V | 85 | |
| Clock Frequency except for fast read DTR and read (03h), Vcc=2.3V~3.6V | fCT | 0 | 104 | MHz | Vcc=2.3V~3.6V | 85 | |
| Clock Frequency for fast read DTR | fCT | 0 | 66 | MHz | SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR | 85 | |
| Clock Frequency for read (03h) | fC | 0 | 50 | MHz | 85 | ||
| CE# High Time | tCEH | 7 | ns | 85 | |||
| CE# Setup Time | tCS | 6 | ns | 85 | |||
| CE# Hold Time | tCH | 6 | ns | 85 | |||
| Data In Setup Time | tDS | 2 | ns | STR | 85 | ||
| Data In Setup Time | tDS | 1.5 | ns | DTR | 85 | ||
| Data in Hold Time | tDH | 2 | ns | STR | 85 | ||
| Data in Hold Time | tDH | 1.5 | ns | DTR | 85 | ||
| Output Valid | tV | 7 | ns | @ 133MHz (CL = 15pF) | 85 | ||
| Output Valid | tV | 8 | ns | @ 104MHz (CL = 30pF) | 85 | ||
| Output Hold Time | tOH | 2 | ns | 85 | |||
| Output Disable Time | tDIS | 8 | ns | 85 | |||
| Sector Erase Time (4Kbyte) | tEC | 70 | 300 | ms | 85 | ||
| Block Erase Time (32Kbyte) | tEC | 0.1 | 0.5 | s | 85 | ||
| Block Erase time (64Kbyte) | tEC | 0.15 | 1 | s | 85 | ||
| Chip Erase Time | 16 | 45 | s | 85 | |||
| Page Program Time | tPP | 0.2 | 0.8 | ms | 85 | ||
| Write Status Register time | tW | 2 | 15 | ms | 86 | ||
| Endurance | 100000 | cycles | JEDEC Standard A117 | 90 |
CAD (KiCad official)
- Symbol:
IS25LP064A-JLLE - Footprint:
Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm - 3D model: WSON-8-EP(6x8) (KiCad packages3D, STEP)
- 3D model files:
is25lp064a-jlle-etched.step/is25lp064a-jlle-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);is25lp064a-jlle.step/is25lp064a-jlle.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ISSI(Integrated Silicon Solution) datasheet (100 pp, sha256
4074cf7f6cbd0d73, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IS25LP064A-JLLE
**ISSI(Integrated Silicon Solution)** · Pre-ordered Chips · WSON-8-EP(6x8)
IS25LP064A-JLLE from ISSI(Integrated Silicon Solution), in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable (CE#) selects the device when low and deselects it when high, with outputs in high impedance; after power-up CE# must transition from high to low before a new instruction is accepted. |
| 2 | SO (IO1) | bidirectional | Serial Data Output (SO/IO1) reads data or status on the falling edge of SCK in standard SPI and acts as bidirectional IO1 in Dual and Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect (WP#/IO2) write-protects the Status Register together with the SRWD bit when pulled low and becomes IO2 when QE is set to 1. |
| 4 | GND | power_in | Ground: connect to ground when referenced to Vcc. |
| 5 | SI (IO0) | bidirectional | Serial Data Input (SI/IO0) writes instructions, addresses or data on the rising edge of SCK in standard SPI and acts as bidirectional IO0 in Dual and Quad SPI modes. |
| 6 | SCK | input | Serial Data Clock (SCK) provides the synchronized clock for input and output timing operations. |
| 7 | HOLD# (IO3) | bidirectional | HOLD# (IO3) is active low and pauses serial communication without resetting the sequence when CE# is low, becoming IO3 when QE is set to 1; the pin defaults to HOLD# (RESET# only on the optional part). |
| 8 | Vcc | power_in | Power: device core power supply. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI(Integrated Silicon Solution) |
| Package | WSON-8-EP(6x8) |
| Category | Interface ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | | -65 | | 150 | °C | | 82 |
| Surface Mount Lead Soldering Temperature - Standard Package | | | | 240 | °C | 3 Seconds, standard package | 82 |
| Surface Mount Lead Soldering Temperature - Lead-free Package | | | | 260 | °C | 3 Seconds, lead-free package | 82 |
| Input Voltage with Respect to Ground on All Pins | | -0.5 | | | V | Max VCC + 0.5V | 82 |
| All Output Voltage with Respect to Ground | | -0.5 | | | V | Max VCC + 0.5V | 82 |
| VCC Supply Voltage | VCC | -0.5 | | 6 | V | | 82 |
| Electrostatic Discharge Voltage (Human Body Model) | | -2000 | | 2000 | V | ANSI/ESDA/JEDEC JS-001 | 82 |
| Operating Temperature (Extended Grade E) | | -40 | | 105 | °C | | 82 |
| VCC Power Supply (2.7V to 3.6V band) | VCC | 2.7 | 3 | 3.6 | V | Max. 133MHz | 82 |
| VCC Power Supply (2.3V to 3.6V band) | VCC | 2.3 | 3 | 3.6 | V | Max. 104MHz | 82 |
| VCC Active Read Current | ICC1 | | 5 | 9 | mA | NORD at 50MHz | 83 |
| VCC Active Read Current | ICC1 | | 7 | 11 | mA | FRD Single at 133MHz | 83 |
| VCC Active Read Current | ICC1 | | 10 | 14 | mA | FRD Quad at 133MHz | 83 |
| VCC Program Current | ICC2 | | 17 | 25 | mA | CE# = VCC, 85°C | 83 |
| VCC Program Current | ICC2 | | | 25 | mA | CE# = VCC, 105°C | 83 |
| VCC WRSR Current | ICC3 | | 17 | 25 | mA | CE# = VCC, 85°C | 83 |
| VCC WRSR Current | ICC3 | | | 25 | mA | CE# = VCC, 105°C | 83 |
| VCC Erase Current (SER/BER32K/BER64K) | ICC4 | | 17 | 25 | mA | CE# = VCC, 85°C | 83 |
| VCC Erase Current (SER/BER32K/BER64K) | ICC4 | | | 25 | mA | CE# = VCC, 105°C | 83 |
| VCC Erase Current (CE) | ICC5 | | 17 | 25 | mA | CE# = VCC, 85°C | 83 |
| VCC Erase Current (CE) | ICC5 | | | 25 | mA | CE# = VCC, 105°C | 83 |
| VCC Standby Current CMOS | ISB1 | | 10 | 20 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 83 |
| VCC Standby Current CMOS | ISB1 | | | 35 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 83 |
| VCC Standby Current CMOS | ISB1 | | | 60 | µA | CE# = VCC, VIN = GND or VCC, 125°C | 83 |
| Deep power down current | ISB2 | | 5 | 10 | µA | CE# = VCC, VIN = GND or VCC, 85°C | 83 |
| Deep power down current | ISB2 | | | 20 | µA | CE# = VCC, VIN = GND or VCC, 105°C | 83 |
| Deep power down current | ISB2 | | | 30 | µA | CE# = VCC, VIN = GND or VCC, 125°C | 83 |
| Input Leakage Current | ILI | -1 | | 1 | µA | VIN = 0V to VCC | 83 |
| Output Leakage Current | ILO | -1 | | 1 | µA | VIN = 0V to VCC | 83 |
| Input Low Voltage | VIL | -0.5 | | | V | Max 0.3VCC | 83 |
| Output Low Voltage | VOL | | | 0.2 | V | VMIN < VCC < VMAX, IOL = 100 µA | 83 |
| Input Capacitance (CE#, SCK) | CIN | | | 6 | pF | VIN = 0V | 84 |
| Input/Output Capacitance (other pins) | CIN/OUT | | | 8 | pF | VIN/OUT = 0V | 84 |
| Clock Frequency except for fast read DTR and read (03h), Vcc=2.7V~3.6V | fCT | 0 | | 133 | MHz | Vcc=2.7V~3.6V | 85 |
| Clock Frequency except for fast read DTR and read (03h), Vcc=2.3V~3.6V | fCT | 0 | | 104 | MHz | Vcc=2.3V~3.6V | 85 |
| Clock Frequency for fast read DTR | fCT | 0 | | 66 | MHz | SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR | 85 |
| Clock Frequency for read (03h) | fC | 0 | | 50 | MHz | | 85 |
| CE# High Time | tCEH | 7 | | | ns | | 85 |
| CE# Setup Time | tCS | 6 | | | ns | | 85 |
| CE# Hold Time | tCH | 6 | | | ns | | 85 |
| Data In Setup Time | tDS | 2 | | | ns | STR | 85 |
| Data In Setup Time | tDS | 1.5 | | | ns | DTR | 85 |
| Data in Hold Time | tDH | 2 | | | ns | STR | 85 |
| Data in Hold Time | tDH | 1.5 | | | ns | DTR | 85 |
| Output Valid | tV | | | 7 | ns | @ 133MHz (CL = 15pF) | 85 |
| Output Valid | tV | | | 8 | ns | @ 104MHz (CL = 30pF) | 85 |
| Output Hold Time | tOH | 2 | | | ns | | 85 |
| Output Disable Time | tDIS | | | 8 | ns | | 85 |
| Sector Erase Time (4Kbyte) | tEC | | 70 | 300 | ms | | 85 |
| Block Erase Time (32Kbyte) | tEC | | 0.1 | 0.5 | s | | 85 |
| Block Erase time (64Kbyte) | tEC | | 0.15 | 1 | s | | 85 |
| Chip Erase Time | | | 16 | 45 | s | | 85 |
| Page Program Time | tPP | | 0.2 | 0.8 | ms | | 85 |
| Write Status Register time | tW | | 2 | 15 | ms | | 86 |
| Endurance | | 100000 | | | cycles | JEDEC Standard A117 | 90 |
## CAD (KiCad official)
- Symbol: `IS25LP064A-JLLE`
- Footprint: `Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm`
- 3D model: WSON-8-EP(6x8) (KiCad packages3D, STEP)
- 3D model files: `is25lp064a-jlle-etched.step` / `is25lp064a-jlle-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `is25lp064a-jlle.step` / `is25lp064a-jlle.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ISSI(Integrated Silicon Solution) datasheet](docs/is25lp064a-jlle-datasheet.pdf) (100 pp, sha256 `4074cf7f6cbd0d73`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/is25lp064a-jlle-datasheet.pdf)