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IS25LP016D-JNLE
Public Made by Adomby adom
ISSI(Integrated Silicon Solution) Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIS25LP016D-JNLE
ISSI(Integrated Silicon Solution) · Pre-ordered Chips · SOIC-8
IS25LP016D-JNLE from ISSI(Integrated Silicon Solution), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable CE# selects the device when pulled low; when high the device is deselected, outputs are high impedance and it enters its low power state. |
| 2 | SO (IO1) | bidirectional | Serial Output SO reads data or status on the falling edge of SCK in standard SPI and becomes bidirectional IO1 in Dual and Quad SPI. |
| 3 | WP# (IO2) | bidirectional | Write Protect WP# protects the Status Register together with the SRWD bit when pulled low, and is unavailable for this function when QE is set to 1 because it becomes IO2. |
| 4 | GND | power_in | Ground: connect to ground when referenced to Vcc. |
| 5 | SI (IO0) | bidirectional | Serial Input SI writes instructions, addresses or data on the rising edge of SCK in standard SPI and becomes bidirectional IO0 in Dual and Quad SPI. |
| 6 | SCK | input | Serial Data Clock SCK is the synchronized clock for input and output timing operations. |
| 7 | HOLD# or RESET# (IO3) | bidirectional | HOLD# (active low, default) pauses serial communication without resetting the sequence, or RESET# driven low puts the memory in reset with output High-Z, selected by the P7 bit; it becomes IO3 when QE is 1. |
| 8 | Vcc | power_in | Power: device core power supply, 2.30V to 3.60V for IS25LP or 1.65V to 1.95V for IS25WP. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI(Integrated Silicon Solution) |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
IS25LP016D-JNLE - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
is25lp016d-jnle-etched.step/is25lp016d-jnle-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);is25lp016d-jnle.step/is25lp016d-jnle.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ISSI(Integrated Silicon Solution) datasheet (115 pp, sha256
b7472bc6861b38f4, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).