IS25LP016D-JLLE from ISSI(Integrated Silicon Solution), in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE#	input	Chip Enable input: driving it high deselects the device and puts outputs in high impedance, and after power-up CE# must transition from high to low before a new instruction is accepted.
2	SO (IO1)	bidirectional	Serial Data Output in standard SPI, read on the falling edge of SCK, and bidirectional IO1 in Dual and Quad SPI modes; SO goes high impedance when HOLD# is low while CE# is low.
3	WP# (IO2)	bidirectional	Write Protect input that, together with the SRWD bit, write-protects the Status Register when pulled low, and becomes bidirectional IO2 when the QE bit is set to 1.
4	GND	power_in	Ground: connect to ground when referenced to Vcc.
5	SI (IO0)	bidirectional	Serial Data Input in standard SPI, latched on the rising edge of SCK, and bidirectional IO0 in Dual and Quad SPI modes.
6	SCK	input	Serial Data Clock input that synchronizes input and output timing; the device supports SPI modes 0 (0,0) and 3 (1,1).
7	HOLD# or RESET# (IO3)	bidirectional	HOLD# is active low and pauses serial communication while CE# is low (default, P7=0), RESET# is selected by P7=1 when QE=0, and the pin becomes IO3 when QE=1.
8	Vcc	power_in	Device core power supply; the IS25LP part operates from 2.30V to 3.60V.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	ISSI(Integrated Silicon Solution)
Package	WSON-8-EP(6x8)
Category	Memory
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature		-65		150	°C		93
Input Voltage with Respect to Ground on All Pins		-0.5			V		93
All Output Voltage with Respect to Ground		-0.5			V		93
VCC	VCC	-0.5		6	V	IS25LP	93
Electrostatic Discharge Voltage (Human Body Model)		-2000		2000	V	Human Body Model	93
VCC Power Supply	VCC	2.3	3	3.6	V	IS25LP	93
Ambient Operating Temperature		-40		105	°C	Extended Grade E	93
VCC Active Read current	ICC1		4	12	mA	NORD at 50MHz	94
VCC Active Read current	ICC1		6	14	mA	FRD Single at 133MHz	94
VCC Active Read current	ICC1		8	15	mA	FRD Dual at 133MHz	94
VCC Active Read current	ICC1		10	17	mA	FRD Quad at 133MHz	94
VCC Active Read current	ICC1		9	16	mA	FRD Quad at 104MHz	94
VCC Program Current	ICC2			25	mA	CE# = VCC, 105°C	94
VCC WRSR Current	ICC3			25	mA	CE# = VCC, 105°C	94
VCC Erase Current (SER/BER32/BER64)	ICC4			25	mA	CE# = VCC, 105°C	94
VCC Erase Current (CE)	ICC5			25	mA	CE# = VCC, 105°C	94
VCC Standby Current	ISB1			20	µA	CMOS CE# = VCC, VIN = GND or VCC, 105°C	94
Deep power down current (IS25LP)	ISB2			15	µA	IS25LP CE# = VCC, VIN = GND or VCC, 105°C	94
Input Leakage Current	ILI	-1		1	µA	VIN = 0V to VCC	94
Output Leakage Current	ILO	-1		1	µA	VIN = 0V to VCC	94
Input Low Voltage	VIL	-0.5			V		94
Output Low Voltage	VOL			0.2	V	IOL = 100 µA	94
Clock Frequency except for fast read Quad I/O, QPI, DTR and read (03h)	fCT	0		133	MHz		96
Clock Frequency for fast read Quad I/O and QPI	fCT	0		133	MHz	IS25LP	96
Clock Frequency for fast read DTR	fCT	0		66	MHz	SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR	96
Clock Frequency for read (03h)	fC	0		50	MHz		96
CE# High Time	tCEH	7			ns		96
CE# Setup Time	tCS	5			ns		96
CE# Hold Time	tCH	5			ns		96
CE# Not Active Hold Time	tCHSL	2.7			ns		96
CE# Not Active Setup Time	tSHCH	2.7			ns		96
Data In Setup Time	tDS	2			ns	STR	96
Data In Setup Time	tDS	1.5			ns	DTR	96
Data In Hold Time	tDH	2			ns	STR	96
Data In Hold Time	tDH	1.5			ns	DTR	96
Output Valid @133MHz	tV			7	ns	CL = 15pF	96
Output Hold Time	tOH	2			ns		96
Output Disable Time	tDIS			8	ns		96
HOLD Active Setup Time relative to SCK	tHLCH	2			ns		96
HOLD Active Hold Time relative to SCK	tCHHH	2			ns		96
HOLD Not Active Setup Time relative to SCK	tHHCH	2			ns		96
HOLD Not Active Hold Time relative to SCK	tCHHL	2			ns		96
HOLD to Output Low Z	tLZ			12	ns		96
HOLD to Output High Z	tHZ			12	ns		96
Sector Erase Time (4Kbyte)	tEC		70	300	ms		96
Block Erase Time (32Kbyte)			0.1	0.5	s		96
Block Erase Time (64Kbyte)			0.15	1	s		96
Chip Erase Time (16Mb)			4	12			96
Page Program Time	tPP		0.2	0.8	ms		96
Release deep power down (IS25LP)	tRES1			3	µs	IS25LP	97
Deep power down	tDP			3	µs		97
Write Status Register time	tW		2	15	ms		97
Suspend to read ready	tSUS	100			µs		97
Resume to next suspend	TRS	80			µs		97
Software Reset recovery time	tSRST			35	µs		97
Hardware Reset recovery time	tHWRST			35	µs		97

CAD (KiCad official)

Symbol: IS25LP016D-JLLE
Footprint: Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm
3D model: WSON-8-EP(6x8), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: is25lp016d-jlle-etched.step / is25lp016d-jlle-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp016d-jlle.step / is25lp016d-jlle.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ISSI(Integrated Silicon Solution) datasheet (115 pp, sha256 b7472bc6861b38f4, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

IS25LP016D-JLLE

Verified IS25LP016D-JLLE

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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