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IS25LP010E-JNLE-TR

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ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IS25LP010E-JNLE-TR

ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8

IS25LP010E-JNLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: when CE# is high the device is deselected, outputs are high impedance and it enters low-power standby; after power-up CE# must go high-to-low before a new instruction is accepted.
2 SO (IO1) bidirectional Serial Data Output in standard SPI, read on the falling edge of SCK; becomes bidirectional IO1 in Dual and Quad SPI and QPI modes.
3 WP# (IO2) bidirectional Write Protect: with SRWD set to 1 and WP# pulled low, the Status Register bits (SRWD, QE, BP3-BP0) are write-protected; it becomes IO2 in Quad SPI and the write-protect function is unavailable when QE is 1.
4 GND power_in Ground: connect to ground when referenced to Vcc.
5 SI (IO0) bidirectional Serial Data Input in standard SPI, latched on the rising edge of SCK; becomes bidirectional IO0 in Dual and Quad SPI and QPI modes.
6 SCK input Serial Clock: synchronizes the input and output timing operations.
7 HOLD# (IO3) bidirectional Hold: when pulled low with CE# low, pauses serial communication without resetting the sequence and puts SO in high impedance; it becomes IO3 when QE is set to 1 and the HOLD# function is unavailable.
8 Vcc power_in Power: device core power supply.

Key specifications

Parameter Value
Manufacturer ISSI Integrated Silicon Solution
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Active Read current, NORD ICC1 6 8 mA NORD at 50MHz 78
VCC Active Read current, FRD Single ICC1 7 9 mA FRD Single at 104MHz 78
VCC Active Read current, FRD Dual ICC1 8 10 mA FRD Dual at 104MHz 78
VCC Active Read current, FRD Quad ICC1 10 12 mA FRD Quad at 104MHz 78
VCC Program Current ICC2 15 20 mA CE# = VCC, 85°C 78
VCC Program Current ICC2 20 mA CE# = VCC, 105°C 78
VCC WRSR Current ICC3 15 20 mA CE# = VCC, 85°C 78
VCC WRSR Current ICC3 20 mA CE# = VCC, 105°C 78
VCC Erase Current (SER/BER4K/BER64K) ICC4 15 20 mA CE# = VCC, 85°C 78
VCC Erase Current (SER/BER4K/BER64K) ICC4 20 mA CE# = VCC, 105°C 78
VCC Erase Current (CE) ICC5 15 20 mA CE# = VCC, 85°C 78
VCC Erase Current (CE) ICC5 20 mA CE# = VCC, 105°C 78
VCC Standby Current CMOS ISB1 17 35 µA CE# = VCC, VIN = GND or VCC, 85°C 78
VCC Standby Current CMOS ISB1 40 µA CE# = VCC, VIN = GND or VCC, 105°C 78
VCC Standby Current CMOS ISB1 45 µA CE# = VCC, VIN = GND or VCC, 125°C 78
Deep power down current (IS25LP) ISB2 6 15 µA CE# = VCC, VIN = GND or VCC, 85°C 78
Deep power down current (IS25LP) ISB2 18 µA CE# = VCC, VIN = GND or VCC, 105°C 78
Deep power down current (IS25LP) ISB2 20 µA CE# = VCC, VIN = GND or VCC, 125°C 78
Input Leakage Current ILI 1 µA VIN = 0V to VCC 78
Output Leakage Current ILO 1 µA VIN = 0V to VCC 78
Input Low Voltage VIL -0.5 V 78
Output Low Voltage VOL 0.2 V VMIN < VCC < VMAX; IOL = 100 µA 78
Ambient Operating Temperature, Extended Grade E -40 105 °C Extended Grade E 77
VCC Power Supply VCC 2.3 3 3.6 V IS25LP 77
Storage Temperature -65 150 °C 77
Surface Mount Lead Soldering Temperature, standard package 240 °C Standard package, 3 seconds 77
Surface Mount Lead Soldering Temperature, lead-free package 260 °C Lead-free package, 3 seconds 77
VCC supply voltage (absolute maximum) VCC -0.5 6 V IS25LP 77
Input voltage with respect to ground on all pins -0.5 V 77
All output voltage with respect to ground -0.5 V 77
Pin capacitance, input (CE#, SCK) CIN 6 pF VIN = 0V, TA = 25°C, VCC = 3V, 1MHz 79
Pin capacitance, input/output (other pins) CIN/OUT 8 pF VIN/OUT = 0V, TA = 25°C, VCC = 3V, 1MHz 79
Clock frequency for fast read mode fCT 0 104 MHz Fast read mode 80
Clock frequency for read mode fC 0 50 MHz Read mode 80
SCK High Time tCKH 4 ns 80
SCK Low Time tCKL 4 ns 80
CE# High Time tCEH 7 ns 80
CE# Setup Time tCS 5 ns 80
CE# Hold Time tCH 5 ns 80
Data In Setup Time tDS 2 ns 80
Data In Hold Time tDH 2 ns 80
Output Valid tV 8 ns 80
Output Hold Time tOH 2 ns 80
Output Disable Time tDIS 8 ns 80
Sector Erase Time (4Kbyte) tEC 70 300 ms 80
Block Erase Time (32Kbyte) 130 500 ms 80
Block Erase Time (64Kbyte) 200 1000 ms Not applicable to 256Kb and 512Kb 80
Chip Erase Time (1Mb) 0.4 1.5 s 1Mb 80
Page Program Time tPP 0.45 1.2 ms 80
Deep power down tDP 3 µs 80
Release deep power down (IS25LP) tres1 3 µs IS25LP 80
Write Status Register time tW 2 10 ms 80
Resume to next suspend tRS 80 µs 80
Suspend to read ready tSUS 100 µs 80
Vcc(min) to CE# Low tVCE 300 µs Vcc(min) to CE# Low 84
Write Inhibit Voltage (IS25LP) VWI 2.1 V IS25LP 84

CAD (KiCad official)

  • Symbol: IS25LP010E-JNLE-TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: is25lp010e-jnle-tr-etched.step / is25lp010e-jnle-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); is25lp010e-jnle-tr.step / is25lp010e-jnle-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ISSI Integrated Silicon Solution datasheet (93 pp, sha256 682d1cb75600d9cd, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF