# IRS2127STRPBF

**Infineon Technologies** · Gate Drive ICs · SOP-8

IRS2127STRPBF from Infineon Technologies, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Logic and gate drive supply, recommended operating range 10 V to 20 V referenced to COM. |
| 2 | IN | input | Logic input for gate driver output HO, in phase with HO for the IRS2127S/IRS21271S, with VIN limited to 0 V to VCC. |
| 3 | FAULT | output | Open-drain, negative-logic indicator that goes low when an over-current shutdown has occurred, with VFLT limited to 0 V to VCC. |
| 4 | COM | power_in | Logic ground, the reference for all absolute voltage ratings. |
| 5 | VS | power_in | High-side floating supply return, rated for offset up to 600 V with logic operational from -5 V to +600 V. |
| 6 | CS | input | Current sense input to the current sense comparator, with CS voltage limited to VS to VS + 5 V and a 250 mV positive-going threshold for this variant. |
| 7 | HO | output | High-side gate drive output referenced to VS, with VHO limited to VS to VB and peak source/sink current of 200 mA / 420 mA. |
| 8 | VB | power_in | High-side floating supply, rated VS + 12 V to VS + 20 V for the IRS2127 variant. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOP-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating supply voltage | VB | -0.3 |  | 625 | V |  | 2 |
| Logic supply voltage | VCC | -0.3 |  | 25 | V |  | 2 |
| Allowable offset supply voltage transient | dVs/dt |  |  | 50 | V/ns |  | 2 |
| Package power dissipation, 8-Lead SOIC | PD |  |  | 0.625 | W | @ TA ≤ +25 °C | 2 |
| Thermal resistance, junction to ambient, 8-Lead SOIC | RthJA |  |  | 200 | °C/W | 8-Lead SOIC | 2 |
| Junction temperature | TJ |  |  | 150 | °C |  | 2 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 2 |
| Lead temperature | TL |  |  | 300 | °C | soldering, 10 seconds | 2 |
| High-side floating supply voltage (IRS2127/IRS2128) | VB | 12 |  | 20 | V | VS + 12 to VS + 20, IRS2127/IRS2128 | 2 |
| High-side floating offset voltage | VS |  |  | 600 | V | Note 1: logic operational for VS of -5 V to +600 V | 2 |
| Logic supply voltage | VCC | 10 |  | 20 | V |  | 2 |
| Logic input voltage | VIN | 0 |  |  | V |  | 2 |
| FAULT output voltage | VFLT | 0 |  |  | V |  | 2 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 2 |
| Logic "0" input voltage (IRS2127/IRS21271) | VIL |  |  | 0.8 | V | VCC = 10 V to 20 V | 3 |
| CS input positive going threshold (IRS2127/IRS2128) | VCSTH+ | 180 | 250 | 320 | mV |  | 3 |
| Offset supply leakage current | ILK |  |  | 50 | µA | VB = VS = 600 V | 3 |
| Quiescent VBS supply current | IQBS |  | 300 | 800 | µA |  | 3 |
| Quiescent VCC supply current | IQCC |  | 60 | 120 | µA |  | 3 |
| Logic "1" input bias current | IIN+ |  | 7 | 15 | µA | VIN = 5 V | 3 |
| Logic "0" input bias current | IIN- |  |  | 5 | µA | VIN = 0 V | 3 |
| "High" CS bias current | ICS+ |  |  | 5 | µA | VCS = 3 V | 3 |
| VBS supply undervoltage positive going threshold (IRS2127/IRS2128) | VBSUV+ | 8.8 | 10.3 | 11.8 | V |  | 3 |
| VBS supply undervoltage negative going threshold (IRS2127/IRS2128) | VBSUV- | 7.5 | 9 | 10.6 | V |  | 3 |
| Output high short circuit pulsed current | IO+ | 200 | 290 |  | mA | VO = 0 V, VIN = 5 V, PW ≤ 10 µs | 3 |
| Output low short circuit pulsed current | IO- | 420 | 600 |  | mA | VO = 15 V, VIN = 0 V, PW ≤ 10 µs | 3 |
| High level output voltage, VBIAS - VO | VOH |  | 0.05 | 0.2 | V |  | 3 |
| Low level output voltage, VO | VOL |  | 0.02 | 0.1 | V |  | 3 |
| Turn-on propagation delay | ton |  | 150 | 200 | ns | VS = 0 V | 3 |
| Turn-off propagation delay | toff |  | 150 | 200 | ns | VS = 600 V | 3 |
| Turn-on rise time | tr |  | 80 | 130 | ns |  | 3 |
| Turn-off fall time | tf |  | 40 | 65 | ns |  | 3 |
| Start-up blanking time | tbl | 550 | 750 | 950 | ns |  | 3 |
| CS shutdown propagation delay | tcs |  | 65 | 360 | ns |  | 3 |
| CS to FAULT pull-up propagation delay | tflt |  | 270 | 510 | ns |  | 3 |
| FAULT - low on resistance | Ron,FLT |  | 125 |  | Ω |  | 3 |

## CAD (KiCad official)

- Symbol: `IRS2127STRPBF`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `irs2127strpbf-etched.step` / `irs2127strpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irs2127strpbf.step` / `irs2127strpbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/irs2127strpbf-datasheet.pdf) (21 pp, sha256 `dfe4bffe9eeffea4`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/irs2127strpbf-datasheet.pdf)