# IRS2106STRPBF

**Infineon Technologies** · Gate Drive ICs · SOIC-8

IRS2106STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side and logic fixed supply, recommended 10 V to 20 V (absolute maximum 25 V). |
| 2 | HIN | input | Logic input for high-side gate driver output HO, in phase, 3.3 V/5 V/15 V logic compatible (VIH min 2.5 V, VIL max 0.8 V). |
| 3 | LIN | input | Logic input for low-side gate driver output LO, in phase, 3.3 V/5 V/15 V logic compatible (VIH min 2.5 V, VIL max 0.8 V). |
| 4 | COM | power_in | Low-side return and logic ground for the IRS2106 (VSS is tied to COM on this 8-lead part). |
| 5 | LO | output | Low-side gate drive output, swings 0 V to VCC. |
| 6 | VS | power_in | High-side floating supply return (offset), operational up to +600 V. |
| 7 | HO | output | High-side gate drive output, swings from VS to VB. |
| 8 | VB | power_in | High-side floating supply, VS + 10 V to VS + 20 V recommended (absolute maximum 625 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating absolute voltage | VB | -0.3 |  | 625 | V |  | 2 |
| Low-side and logic fixed supply voltage | VCC | -0.3 |  | 25 | V |  | 2 |
| Allowable offset supply voltage transient | dVS/dt |  |  | 50 | V/ns |  | 2 |
| Package power dissipation (8 lead SOIC) | PD |  |  | 0.625 | W | @ TA ≤ +25 °C | 2 |
| Thermal resistance, junction to ambient (8 lead SOIC) | RthJA |  |  | 200 | °C/W |  | 2 |
| Junction temperature | TJ |  |  | 150 | °C |  | 2 |
| Storage temperature | TS | -50 |  | 150 | °C |  | 2 |
| Lead temperature (soldering, 10 seconds) | TL |  |  | 300 | °C |  | 2 |
| High-side floating supply offset voltage | VS |  |  | 600 | V | Note 1 | 3 |
| Low-side and logic fixed supply voltage | VCC | 10 |  | 20 | V |  | 3 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 3 |
| Turn-on propagation delay | ton |  | 220 | 300 | ns | VS = 0 V | 3 |
| Turn-off propagation delay | toff |  | 200 | 280 | ns | VS = 0 V or 600 V | 3 |
| Delay matching, HS & LS turn-on/off | MT |  | 0 | 30 | ns |  | 3 |
| Turn-on rise time | tr |  | 100 | 220 | ns |  | 3 |
| Turn-off fall time | tf |  | 35 | 80 | ns |  | 3 |
| Logic "1" input voltage | VIH | 2.5 |  |  | V |  | 4 |
| Logic "0" input voltage | VIL |  |  | 0.8 | V |  | 4 |
| High level output voltage, VBIAS - VO | VOH |  | 0.05 | 0.2 | V | IO = 2 mA | 4 |
| Low level output voltage, VO | VOL |  | 0.02 | 0.1 | V | IO = 2 mA | 4 |
| Offset supply leakage current | ILK |  |  | 50 | µA | VB = VS = 600 V | 4 |
| Quiescent VBS supply current | IQBS | 20 | 75 | 130 | µA | VIN = 0 V or 5 V | 4 |
| Quiescent VCC supply current | IQCC | 60 | 120 | 180 | µA | VIN = 0 V or 5 V | 4 |
| Logic "1" input bias current | IIN+ |  | 5 | 20 | µA | VIN = 5 V | 4 |
| Logic "0" input bias current | IIN- |  |  | 5 | µA | VIN = 0 V | 4 |
| VCC and VBS supply undervoltage positive going threshold | VCCUV+/VBSUV+ | 8 | 8.9 | 9.8 | V |  | 4 |
| VCC and VBS supply undervoltage negative going threshold | VCCUV-/VBSUV- | 7.4 | 8.2 | 9 | V |  | 4 |
| Hysteresis | VCCUVH/VBSUVH | 0.3 | 0.7 |  | V |  | 4 |
| Output high short circuit pulsed current | IO+ | 130 | 290 |  | mA | VO = 0 V, PW ≤ 10 µs | 4 |
| Output low short circuit pulsed current | IO- | 270 | 600 |  | mA | VO = 15 V, PW ≤ 10 µs | 4 |

## CAD (KiCad official)

- Symbol: `IRS2106STRPBF`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `irs2106strpbf-etched.step` / `irs2106strpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irs2106strpbf.step` / `irs2106strpbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/irs2106strpbf-datasheet.pdf) (25 pp, sha256 `b2665cb576bf9e31`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/irs2106strpbf-datasheet.pdf)