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IRS2005STR

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UMW Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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irs2005str-hero.glb irs2005str: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
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IRS2005STR

UMW · Gate Drivers · SOP-8

IRS2005STR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side and logic fixed supply; recommended operating range is 10 V to 20 V, with absolute maximum 25 V (-0.3 V to 25 V).
2 HIN input Logic input for the high-side gate driver output (HO), in phase; logic-high threshold is 2.5 V minimum and logic-low is 0.8 V maximum, with input range 0 V to VCC.
3 LIN input Logic input for the low-side gate driver output (LO), in phase; logic-high threshold is 2.5 V minimum and logic-low is 0.8 V maximum, with input range 0 V to VCC.
4 VSS power_in Low-side return; all voltage ratings in the datasheet are referenced to VSS.
5 LO output Low-side gate drive output, swinging between 0 V and VCC, with typical pulsed source/sink capability of 290 mA/600 mA.
6 VS power_in High-side floating supply return; recommended range is -9 V to 250 V, and the datasheet notes IC operation is ensured only for VS between -8 V and 200 V.
7 HO output High-side gate drive output, swinging between VS and VB.
8 VB power_in High-side floating supply; recommended range is VS + 10 V to VS + 20 V, with absolute maximum 275 V.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High side floating supply voltage (absolute max) VB -0.3 275 V 3
Low side gate drive output voltage (absolute max) VLO -0.3 V 3
Logic input voltage HIN & LIN (absolute max) VIN -0.3 V 3
Low side and main power supply (absolute max) VCC -0.3 25 V Note1: all power supplies tested at 25V 3
Allowable Offset Supply Voltage Transient dVS/dt 50 V/ns 3
ESD HBM Model 1500 V 3
ESD Machine Model 500 V 3
Package Power Dissipation PD 625 mW TA ≤25°C 3
Thermal Resistance, Junction to Ambient RthJA 200 °C/W 3
Junction Temperature TJ 150 3
Storage Temperature TS -55 150 °C 3
Lead Temperature (Soldering) TL 300 10 seconds 3
High side floating supply return (recommended) VS -9 250 V Note2: VS between -8V and 200V ensures IC works 3
Low side and main power supply (recommended) VCC 10 20 V 3
Low side gate drive output voltage (recommended) VLO 0 V 3
Logic input voltage HIN & LIN (recommended) VIN 0 V 3
Ambient temperature TA -40 125 °C 3
Turn-on propagation delay tON 130 200 ns VS=0/250V 4
Turn-off propagation delay tOFF 130 200 ns VS=0V 4
Turn-on rise time tR 70 170 ns 4
Turn-off fall time tF 30 90 ns 4
Matching delay ON and OFF MT 50 ns 4
VCC supply UVLO threshold (rising) VCCUV+ 8 8.9 9.8 V 4
VCC supply UVLO threshold (falling) VCCUV- 7.4 8.2 9 V 4
VBS supply UVLO threshold (rising) VBSUV+ 8 8.9 9.8 V 4
VBS supply UVLO threshold (falling) VBSUV- 7.4 8.2 9 V 4
High-side floating supply leakage current ILK 50 μA VB=VS=250V 4
Quiescent VB supply current IQBS 50 75 μA VIN=0V 4
Quiescent VCC supply current IQCC 120 250 μA VIN=0V 4
Logic “1” (HIN&LIN) input voltage VIH 2.5 V VCC=10Vto 20V 4
Logic “0” (HIN&LIN) input voltage VIL 0.8 V VCC=10Vto 20V 4
High level output voltage, VBIAS - VO VOH 0.05 0.2 V IO=2mA 4
Low level output voltage, VO VOL 0.02 0.1 V 4
Logic “1” input bias current IIN+ 3 10 μA VIN=5V 4
Logic “0” input bias current IIN- 0 5 μA VIN=0V 4
Output high short circuit pulsed current IO+ 200 290 mA VO=0V, PW≤10us 4
Output low short circuit pulsed current IO- 420 600 mA VO=15V, PW≤10us 4

CAD (KiCad official)

  • Symbol: IRS2005STR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: irs2005str-etched.step / irs2005str-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irs2005str.step / irs2005str.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (8 pp, sha256 996095845be79dc4, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF