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IRS2004STRPBF

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Infineon Technologies Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IRS2004STRPBF

Infineon Technologies · Gate Drivers · SOIC-8

IRS2004STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side and logic fixed supply, recommended 10 V to 20 V with an absolute maximum of -0.3 V to 25 V.
2 IN input Logic input for the high-side and low-side gate driver outputs (HO and LO), in phase with HO, compatible with 3.3 V, 5 V and 15 V logic; VIN is limited to -0.3 V to VCC + 0.3 V.
3 SD input Logic input for shutdown that turns off both channels; the positive-going threshold is at least 2.5 V and the negative-going threshold is at most 0.8 V.
4 COM power_in Low-side return; all voltage parameters in the datasheet are referenced to COM.
5 LO output Low-side gate drive output, swinging between 0 V and VCC.
6 VS power_in High-side floating supply return; the offset is rated up to 200 V and logic operates for VS of -5 V to +200 V, with an absolute range of VB - 25 V to VB + 0.3 V.
7 HO output High-side gate drive output, referenced to VS and swinging between VS and VB.
8 VB power_in High-side floating supply, recommended VS + 10 V to VS + 20 V with an absolute maximum of -0.3 V to 225 V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-side and logic fixed supply voltage (absolute maximum) VCC -0.3 25 V 2
Low-side output voltage (absolute maximum, min) VLO -0.3 V 2
Logic input voltage (IN & SD) (absolute maximum, min) VIN -0.3 V 2
High-side floating absolute voltage VB -0.3 225 V 2
Allowable offset supply voltage transient dVs/dt 50 V/ns 2
Package power dissipation (8 lead SOIC) PD 0.625 W TA ≤ +25 °C 2
Thermal resistance, junction to ambient (8 lead SOIC) RthJA 200 °C/W 2
Junction temperature TJ 150 °C 2
Storage temperature TS -55 150 °C 2
Lead temperature (soldering, 10 seconds) TL 300 °C 10 seconds 2
Low-side and logic fixed supply voltage (recommended) VCC 10 20 V 2
High-side floating supply offset voltage (recommended, max) VS 200 V 2
Ambient temperature (recommended) TA -40 125 °C 2
Low-side output voltage (recommended, min) VLO 0 V 2
Logic input voltage (IN & SD) (recommended, min) VIN 0 V 2
Logic "1" (HO) & Logic "0" (LO) input voltage VIH 2.5 V 3
Logic "0" (HO) & Logic "1" (LO) input voltage VIL 0.8 V 3
SD input positive going threshold VSD,TH+ 2.5 V 3
SD input negative going threshold VSD,TH- 0.8 V 3
High level output voltage, VBIAS - VO VOH 0.05 0.2 V 3
Low level output voltage, VO VOL 0.02 0.1 V 3
Offset supply leakage current ILK 50 µA VB = VS = 200 V 3
Quiescent VBS supply current IQBS 30 55 µA 3
Quiescent VCC supply current IQCC 150 270 µA 3
Logic "1" input bias current IIN+ 3 10 µA VIN = 5 V 3
Logic "0" input bias current IIN- 5 µA VIN = 0 V 3
VCC supply undervoltage positive going threshold VCCUV+ 8 8.9 9.8 V 3
VCC supply undervoltage negative going threshold VCCUV- 7.4 8.2 9 V 3
Output high short circuit pulsed current IO+ 130 290 mA VO = 0 V, PW ≤ 10 µs 3
Output low short circuit pulsed current IO- 270 600 mA VO = 15 V, PW ≤ 10 µs 3
Turn-on propagation delay ton 680 820 ns VS = 0 V 3
Turn-off propagation delay toff 150 220 ns VS = 200 V 3
Shutdown propagation delay tsd 160 220 ns 3
Turn-on rise time tr 70 170 ns 3
Turn-off fall time tf 35 90 ns 3
Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off DT 400 520 650 ns HS turn-on to LS turn-off 3
Delay matching, HS & LS turn-on/off MT 60 ns 3

CAD (KiCad official)

  • Symbol: IRS2004STRPBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: irs2004strpbf-etched.step / irs2004strpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irs2004strpbf.step / irs2004strpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (15 pp, sha256 6a7ad8deb2da0c27, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF