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IRS2003STR

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UMW Gate Drivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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irs2003str-hero.glb irs2003str: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
irs2003str-hero.overlay.json Publish 0.1.0 · Ray 7d ago
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irs2003str.step Publish 0.1.0 · Ray 7d ago
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IRS2003STR

UMW · Gate Drivers · SOP-8

IRS2003STR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low side and logic fixed supply, recommended operating range 10 V to 20 V referenced to VSS.
2 HIN input Logic input for the high side gate driver output (HO), in phase; accepts 3.3 V, 5 V and 15 V logic, with recommended range 0 to VCC.
3 LIN input Logic input for the low side gate driver output (LO), out of phase; accepts 3.3 V, 5 V and 15 V logic, with recommended range 0 to VCC.
4 VSS power_in Low side return, the reference for all voltage parameters, rated at 0 V in the recommended operating conditions.
5 LO output Low side gate drive output, with a recommended range of 0 V to VCC.
6 VS power_in High side floating supply return, with a recommended range of -9 V to 250 V and an allowable negative transient of -9 V.
7 HO output High side gate drive output, with a recommended range of VS to VB.
8 VB power_in High side floating supply, with a recommended range of VS + 10 V to VS + 20 V.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High side floating supply voltage VB -0.3 275 V 4
Low side and main power supply VCC -0.3 25 V Note1: all power supplies tested at 25V 4
Low side gate drive output VLO -0.3 V 4
Logic input of HIN & LIN VIN -0.3 V 4
Allowable offset supply voltage transient dVS/dt 50 V/ns 4
ESD HBM model ESD 1500 V HBM model; value printed in the Min column of the ESD table 4
ESD machine model ESD 500 V Machine model; value printed in the Min column of the ESD table 4
Package power dissipation PD1 625 mW TA ≤25°C 4
High side floating supply return VS -9 250 V Note2: transient negative VS to VSS-50V, 50ns pulse width, guaranteed by design 5
Low side and main power supply VCC 10 20 V 5
Low side gate drive output VLO 0 V 5
Logic input of HIN & LIN VIN 0 V 5
Ambient temperature TA -40 125 °C 5
Thermal resistance, junction to ambient RthJA 200 °C/W 5
Junction temperature TJ 150 °C 5
Storage temperature TS -55 150 °C 5
Lead temperature (soldering) TL 300 °C Soldering, 10 seconds 5

CAD (KiCad official)

  • Symbol: IRS2003STR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: irs2003str-etched.step / irs2003str-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irs2003str.step / irs2003str.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (12 pp, sha256 6afc2c169a806197, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF