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IRMCF341TY

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Infineon Technologies Motor Driver ICs, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsirmcf341tyfactory-2.0.0extractor-text

Verified IRMCF341TY

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: IRMCF341TY · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C538212, digikey 448-IRMCF341TY-ND, mouser 942-IRMCF341TY
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-2xa7ctuz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ irmcf341ty.kicad_sym✓ irmcf341ty.kicad_mod✓ irmcf341ty.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers irmcf341ty: viewers · Ray 8d ago
irmcf341ty-etched.glb Publish 0.1.0 · Ray 8d ago
irmcf341ty-etched.step irmcf341ty: factory component page (tier=lcsc) · Ray 8d ago
irmcf341ty-hero.glb irmcf341ty: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
irmcf341ty-hero.overlay.json Publish 0.1.0 · Ray 8d ago
irmcf341ty.glb Publish 0.1.0 · Ray 8d ago
irmcf341ty.kicad_mod Publish 0.1.0 · Ray 8d ago
irmcf341ty.kicad_sym Publish 0.1.0 · Ray 8d ago
irmcf341ty.lbr Publish 0.1.0 · Ray 8d ago
irmcf341ty.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
verification.json Verified: Published by the parts factory: tier lcsc, 64 pins · Ray 8d ago

IRMCF341TY

Infineon Technologies · Motor Driver ICs · LQFP-64(10x10)

IRMCF341TY from Infineon Technologies, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTAL0 input Crystal input; crystal frequency 3.2 MHz min to 60 MHz max.
2 XTAL1 output Crystal output.
3 P1.0/T2 bidirectional Discrete programmable I/O or Timer/Counter 2 input.
4 P1.1/RXD bidirectional Discrete programmable I/O or UART receive input.
5 P1.2/TXD bidirectional Discrete programmable I/O or UART transmit output.
6 P1.3/SYNC/SCK bidirectional Discrete programmable I/O, SYNC output or SPI clock output; must be pulled up to VDD1 to boot from I2C EEPROM.
7 P1.4/CAP bidirectional Discrete programmable I/O or Capture timer input.
8 P1.5 bidirectional Discrete programmable I/O.
9 P1.6 bidirectional Discrete programmable I/O.
10 P1.7 bidirectional Discrete programmable I/O.
11 VDD2 power_in 1.8V digital power (core logic, 1.62 V to 1.98 V recommended).
12 VSS power_in Digital common.
13 VDD1 power_in 3.3V digital power (I/O, 3.0 V to 3.6 V recommended).
14 P2.0/NMI bidirectional Discrete programmable I/O or Non-maskable Interrupt input.
15 P2.1 bidirectional Discrete programmable I/O.
16 P2.2 bidirectional Discrete programmable I/O.
17 P2.3 bidirectional Discrete programmable I/O.
18 P2.4 bidirectional Discrete programmable I/O.
19 P2.5 bidirectional Discrete programmable I/O.
20 P2.6/AOPWM0 bidirectional Discrete programmable I/O or PWM 0 digital output (8-bit analog output PWM).
21 P2.7/AOPWM1 bidirectional Discrete programmable I/O or PWM 1 digital output (8-bit analog output PWM).
22 VDD2 power_in 1.8V digital power.
23 VSS power_in Digital common.
24 AIN0 input Analog input channel 0, 0-1.2V range, typically DC bus voltage; pull down to AVSS if unused.
25 AVDD power_in 1.8V analog power (1.71 V to 1.89 V recommended).
26 AVSS power_in Analog common.
27 AIN1 input Analog input channel 1, 0-1.2V range, pull down to AVSS if unused.
28 CMEXT output Unbuffered 0.6V output to the AREF buffer; a capacitor (100 nF in characterization) must be connected.
29 AREF output Analog reference voltage output (0.6V buffered).
30 IFB- input Single shunt current sensing OP amp negative input; feedback resistor of 5 kΩ to 20 kΩ required between IFBO and IFB-.
31 IFB+ input Single shunt current sensing OP amp positive input (0-1.2V input range).
32 IFBO output Single shunt current sensing OP amp output.
33 AIN2 input Analog input channel 2, 0-1.2V range, pull down to AVSS if unused.
34 AIN3 input Analog input channel 3, 0-1.2V range, pull down to AVSS if unused.
35 AIN4 input Analog input channel 4, 0-1.2V range, pull down to AVSS if unused.
36 AIN5 input Analog input channel 5, 0-1.2V range, pull down to AVSS if unused.
37 AIN6 input Analog input channel 6, 0-1.2V range, pull down to AVSS if unused.
38 VDD2 power_in 1.8V digital power.
39 VSS power_in Digital common.
40 VDD1 power_in 3.3V digital power.
41 GATEKILL input PWM shutdown input with 2-μsec digital filter, configurable high or low true; negates all six PWM signals.
42 PWMWL output PWM gate drive for phase W low side, configurable high or low true; 70 kΩ internal pull-up.
43 PWMWH output PWM gate drive for phase W high side, configurable high or low true; 70 kΩ internal pull-up.
44 PWMVL output PWM gate drive for phase V low side, configurable high or low true; 70 kΩ internal pull-up.
45 PWMVH output PWM gate drive for phase V high side, configurable high or low true; 70 kΩ internal pull-up.
46 PWMUL output PWM gate drive for phase U low side, configurable high or low true; 70 kΩ internal pull-up.
47 PWMUH output PWM gate drive for phase U high side, configurable high or low true; 70 kΩ internal pull-up.
48 P3.0/INT2/CS1 bidirectional Discrete programmable I/O, external interrupt 2 input or SPI Chip Select 1.
49 P3.1/AOPWM2 bidirectional Discrete programmable I/O or PWM 2 digital output (8-bit analog output PWM).
50 P3.2/INT0 bidirectional Discrete programmable I/O or Interrupt 0 input.
51 P3.3/INT1 bidirectional Discrete programmable I/O or Interrupt 1 input.
52 P3.5/T1 bidirectional Discrete programmable I/O or Timer/Counter 1.
53 VSS power_in Digital common.
54 VDD1 power_in 3.3V digital power.
55 SCL/SO-SI bidirectional I2C clock output (open drain, needs pull-up) or SPI data.
56 SDA/CS0 bidirectional I2C data (open drain, needs pull-up) or SPI Chip Select 0.
57 P5.1/TMS bidirectional JTAG test mode select (JTAG port by default).
58 P5.2/TDO bidirectional JTAG test data output (JTAG port by default).
59 P5.3/TDI bidirectional JTAG test data input (JTAG port by default).
60 TCK input JTAG test clock.
61 TSTMOD input Test mode pin with 58 kΩ internal pull-down; must be tied to VSS, factory use only.
62 RESET bidirectional Active-low system reset, Schmitt trigger input; needs pull-up to VDD1 but no external RC.
63 PLLVDD power_in 1.8V PLL power (1.62 V to 1.92 V recommended).
64 PLLVSS power_in PLL ground.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package LQFP-64(10x10)
Category Power Management ICs
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD1 (abs max) VDD1 -0.3 3.6 V Respect to VSS 13
Supply Voltage VDD2 (abs max) VDD2 -0.3 1.98 V Respect to VSS 13
Analog Input Voltage VIA -0.3 1.98 V Respect to AVSS 13
Digital Input Voltage VID -0.3 3.65 V Respect to VSS 13
Ambient Temperature TA -40 85 °C 13
Storage Temperature TS -65 150 °C 13
System Clock SYSCLK 32 128 MHz 13
Supply Voltage VDD1 VDD1 3 3.3 3.6 V Recommended 14
Supply Voltage VDD2 VDD2 1.62 1.8 1.98 V Recommended 14
Input Low Voltage VIL -0.3 0.8 V Recommended 14
Input High Voltage VIH 2 3.6 V Recommended 14
Input leakage current IL 1 µA VO = 3.3 V or 0 V 14
Low level output current (SCL/SO-SI, SDA/CS0) IOL1 8.9 13.2 15.2 mA VOL = 0.4 V 14
High level output current (SCL/SO-SI, SDA/CS0) IOH1 12.4 24.8 38 mA VOH = 2.4 V 14
Low level output current (general I/O) IOL2 17.9 26.3 33.4 mA VOL = 0.4 V 14
High level output current (general I/O) IOH2 24.6 49.5 81 mA VOH = 2.4 V 14
Input capacitance CIN 3.6 pF 14
PLL Supply Voltage VPLLVDD 1.62 1.8 1.92 V Recommended 15
Analog Supply Voltage VAVDD 1.71 1.8 1.89 V Recommended 15
Input Offset Voltage VOFFSET 26 mV VAVDD = 1.8 V 15
OP amp feedback resistor RFDBK 5 20 kΩ Requested between IFBO and IFB- 15
Operating Close loop Gain OP GAINCL 80 db 15
UVcc positive going Threshold UVCC+ 1.53 1.66 1.71 V VDD1 = 3.3 V 16
UVcc negative going Threshold UVCC- 1.52 1.62 1.71 V VDD1 = 3.3 V 16
CMEXT voltage VCM 495 600 700 mV VAVDD = 1.8 V 16
Buffer Output Voltage VAREF 495 600 700 mV VAVDD = 1.8 V 16
Crystal input frequency FCLKIN 3.2 4 60 MHz 17
Internal clock frequency FPLL 32 50 128 MHz 17
PLL lock time TLOCK 500 µsec 17
Conversion time TCONV 2.05 µsec 18
Sample/Hold maximum hold time THOLD 10 µsec Voltage droop ≤ 15 LSB 18
OP amp slew rate OPSR 10 V/µsec VAVDD = 1.8 V, CL = 33 pF 19
Settling time TSET 400 ns VAVDD = 1.8 V, CL = 33 pF 19
SYNC to current feedback conversion time tdSYNC1 100 SYSCLK 20
SYNC to AIN0-6 analog input conversion time tdSYNC2 200 SYSCLK 20
SYNC to PWM output delay time tdSYNC3 2 SYSCLK 20
GATEKILL pulse width twGK 32 SYSCLK 21
GATEKILL to PWM output delay tdGK 100 SYSCLK 21
INT0, INT1 Interrupt Assertion Time twINT 4 SYSCLK 21
INT0, INT1 latency tdINT 4 SYSCLK 21
I2C clock period TI2CLK 10 8192 SYSCLK 22
SPI clock period TSPICLK 4 SYSCLK 23
CS to data delay time (write) tCSDELAY 10 nsec 23
CLK falling edge to data delay time tWRDELAY 10 nsec 23
SPI read data setup time tRDSU 10 nsec 24
SPI read data hold time tRDHOLD 10 nsec 24
CAPTURE input period TCAPCLK 8 SYSCLK 26
TCK High Period tJHIGH 10 nsec 27
TCK Low Period tJLOW 10 nsec 27
TCK to TDO propagation delay time tCO 0 5 nsec 27
TDI/TMS setup time tJSETUP 4 nsec 27
TDI/TMS hold time tJHOLD 0 nsec 27

CAD (KiCad official)

  • Symbol: IRMCF341TY
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: irmcf341ty-etched.step / irmcf341ty-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irmcf341ty.step / irmcf341ty.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (32 pp, sha256 808248810f3bd584, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF