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IRMCF188TY

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Infineon Technologies Motor Driver ICs, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsirmcf188tyfactory-2.0.0extractor-text

Verified IRMCF188TY

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: IRMCF188TY · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 38-page datasheet
  • ✓distributor: lcsc C538208, digikey 448-IRMCF188TY-ND, mouser 942-IRMCF188TY
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5_sjrfas/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ irmcf188ty.kicad_sym✓ irmcf188ty.kicad_mod✓ irmcf188ty.step
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Ray Publish 0.1.0 9a90a4d 8d ago

IRMCF188TY

Infineon Technologies · Motor Driver ICs · LQFP-64(10x10)

IRMCF188TY from Infineon Technologies, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTAL0 input Crystal input; pin structure is shown in Figure 27.
2 XTAL1 output Crystal output; pin structure is shown in Figure 27.
3 P1.0/T2 bidirectional Discrete programmable I/O or Timer/Counter 2 input.
4 SCL/SO-SI bidirectional I2C clock output (open drain, needs pull-up) or SPI data, as printed in the pin list.
5 SDA/CS0 bidirectional I2C data (open drain, needs pull-up) or SPI Chip Select 0.
6 P1.3/SYNC/SCK bidirectional Discrete programmable I/O, SYNC output, or SPI clock output.
7 P1.4/CAP bidirectional Discrete programmable I/O or Capture timer input.
8 P1.6 bidirectional Discrete programmable I/O.
9 P1.7 bidirectional Discrete programmable I/O; the pin list leaves the pin type blank for this pin.
10 VDD1 power_in 3.3V digital power.
11 VSS power_in Digital common.
12 VDDCAP power_out Internal 1.8V output; capacitor(s) to be connected.
13 P2.0/NMI bidirectional Discrete programmable I/O or Non-maskable Interrupt input.
14 P3.2/INT0 bidirectional Discrete programmable I/O or Interrupt 0 input.
15 P2.2 bidirectional Discrete programmable I/O.
16 P2.3 bidirectional Discrete programmable I/O.
17 P2.6/AOPWM0 bidirectional Discrete programmable I/O or PWM 0 digital output.
18 P2.7/AOPWM1 bidirectional Discrete programmable I/O or PWM 1 digital output.
19 OP1O output Op amp output for application sensing, 0-1.2V range.
20 OP1- input Op amp negative input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
21 OP1+ input Op amp positive input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
22 VDCBUS input Analog input channel (0-1.2V) allocated for DC bus voltage input; needs to be pulled down to AVSS if unused.
23 AIN1 input Analog input channel 1, 0-1.2V range; needs to be pulled down to AVSS if unused.
24 AIN2 input Analog input channel 2, 0-1.2V range; needs to be pulled down to AVSS if unused.
25 AIN3 input Analog input channel 3, 0-1.2V range; needs to be pulled down to AVSS if unused.
26 AIN4 input Analog input channel 4, 0-1.2V range; needs to be pulled down to AVSS if unused.
27 ADCH input Analog input channel dedicated for A/D compensation (0-1.2V); needs to be pulled down to AVSS if unused.
28 OP2- input Op amp negative input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
29 OP2+ input Op amp positive input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
30 OP2O output Op amp output for application sensing, 0-1.2V range.
31 CMEXT output Unbuffered 0.6V output; a capacitor needs to be connected.
32 AREF output Analog reference voltage output (0.6V).
33 ADCL input Input for A/D compensation (0-1.2V), internally biased to 0.6V; see Figure 23 for internal structure.
34 OP3- input Op amp negative input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
35 OP3+ input Op amp positive input for application sensing, 0-1.2V range; needs to be pulled down to AVSS if unused.
36 OP3O output Op amp output for application sensing, 0-1.2V range.
37 AVSS power_in Analog common.
38 VDDCAP power_out Internal 1.8V output; capacitor(s) to be connected.
39 VDD1 power_in 3.3V digital power.
40 VSS power_in Digital common.
41 P3.1/AOPWM2 bidirectional Discrete programmable I/O or PWM 2 digital output.
42 PWMWL output PWM gate drive for phase W low side, configurable either high or low true; 58 kΩ internal pull-down.
43 PWMVL output PWM gate drive for phase V low side, configurable either high or low true; 58 kΩ internal pull-down.
44 PWMUL output PWM gate drive for phase U low side, configurable either high or low true; 58 kΩ internal pull-down.
45 PWMWH output PWM gate drive for phase W high side, configurable either high or low true; 58 kΩ internal pull-down.
46 P3.7 bidirectional Discrete programmable I/O.
47 P2.1 bidirectional Discrete programmable I/O.
48 PWMVH output PWM gate drive for phase V high side, configurable either high or low true; 58 kΩ internal pull-down.
49 PWMUH output PWM gate drive for phase U high side, configurable either high or low true; 58 kΩ internal pull-down.
50 P1.5 bidirectional Discrete programmable I/O.
51 PFCPWM bidirectional PFC PWM gate drive, configurable either high or low.
52 PFCGKILL input PFCPWM shutdown input, active low; 70 kΩ internal pull-up.
53 GATEKILL input PWM shutdown input, active low, with configurable digital filter; 70 kΩ internal pull-up.
54 P3.0/INT2/CS1 bidirectional Discrete programmable I/O, external interrupt 2 input, or SPI Chip Select 1; 70 kΩ internal pull-up.
55 P5.2/TMS input JTAG test mode select or digital input port.
56 TDO output JTAG test data output.
57 P5.1/TDI input JTAG test data input or digital input port.
58 TCK input JTAG test clock.
59 RESET input Reset, low true, Schmitt trigger input.
60 P1.1/RXD bidirectional UART receiver input or discrete programmable I/O.
61 P1.2/TXD bidirectional UART transmitter output or discrete programmable I/O.
62 P3.4/T0 bidirectional Discrete programmable I/O or Timer/Counter 2 input, as printed in the pin list.
63 P3.5/T1 bidirectional Discrete programmable I/O or Timer/Counter 2 input, as printed in the pin list.
64 P3.3/INT1 bidirectional Interrupt 1 input or discrete I/O.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package LQFP-64(10x10)
Category Power Management ICs
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (recommended) VDD1 3 3.3 3.6 V Recommended 15
System Clock SYSCLK 32 120 MHz VDD1=3.3 V; CAREF=1 nF, CMEXT=100 nF 14
Input Low Voltage VIL -0.3 0.8 V Recommended 15
Input High Voltage VIH 2 3.6 V Recommended 15
Input leakage current (min entry) IL -10 nA VO = 3.3 V or 0 V 15
Input leakage current (max entry) IL -1 1 μA VO = 3.3 V or 0 V 15
Low level output current (IOL1) IOL1 8.9 13.2 15.2 mA VOL = 0.4 V; applies to SCL/SO-SI, SDA/CS0 pins 15
High level output current (IOH1) IOH1 12.4 24.8 38 mA VOH = 2.4 V; applies to SCL/SO-SI, SDA/CS0 pins 15
Low level output current (IOL2) IOL2 17.9 26.3 33.4 mA VOL = 0.4 V; applies to all digital I/O except SCL/SO-SI and SDA/CS0 15
High level output current (IOH2) IOH2 24.6 49.5 81 mA VOH = 2.4 V; applies to all digital I/O except SCL/SO-SI and SDA/CS0 15
Input Offset Voltage VOFFSET 26 mV VAVDD = 1.8 V 16
Input Voltage Range VI 0 1.2 V Recommended 16
OP amp output operating range (min) VOUTSW 50 mV VAVDD = 1.8 V 16
OP amp output operating range (max) VOUTSW 1.2 V VAVDD = 1.8 V 16
OP amp feedback resistor RFDBK 5 20 k Requested between IFBO and IFB-OP 16
Operating Close loop Gain GAINCL 80 db 16
UVcc positive going threshold UVCC+ 2.78 3.04 3.23 V 17
UVcc negative going threshold UVCC- 2.78 2.97 3.23 V 17
CMEXT voltage VCM 495 600 700 mV VVDD1 = 3.3 V 17
AREF buffer output voltage VAREF 495 600 700 mV VVDD1 = 3.3 V 17
Crystal input frequency FCLKIN 3.2 4 60 MHz 18
Internal clock frequency FPLL 32 50 128 MHz 18
PLL lock time TLOCK 500 μsec 18
Conversion time TCONV 2.05 μsec 19
Sample/Hold maximum hold time THOLD 10 μsec Voltage droop ≤ 15 LSB 19
SYNC to current feedback conversion time tdSYNC1 100 SYSCLK 21
SYNC to AIN0-4, ADCH, ADCL conversion time tdSYNC2 200 SYSCLK 21
SYNC to PWM output delay time tdSYNC3 2 SYSCLK 21
GATEKILL pulse width twGK 32 SYSCLK 22
GATEKILL to PWM output delay tdGK 100 SYSCLK 22
Supply voltage VDD1 (absolute maximum) VDD1 -0.3 3.6 V Respect to VSS 14
Analog input voltage (absolute maximum) VIA -0.3 1.98 V Respect to AVSS 14
Digital input voltage (absolute maximum) VID -0.3 6 V Respect to VSS 14
Ambient temperature (absolute maximum) TA -40 125 °C 14
Storage temperature (absolute maximum) TS -65 150 °C 14

CAD (KiCad official)

  • Symbol: IRMCF188TY
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: irmcf188ty-etched.step / irmcf188ty-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irmcf188ty.step / irmcf188ty.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (38 pp, sha256 7e9bead7e1a90f62, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF