component
IRL640STRLPBF
Public Made by Adomby adom
Vishay Intertech MOSFETs, D2PAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IRL640STRLPBF
Vishay Intertech · MOSFETs · D2PAK
IRL640STRLPBF from Vishay Intertech, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate-source voltage is rated at ±10 V (VGS) in the absolute maximum ratings, and the gate input resistance is 0.3 to 1.2 Ω at 1 MHz. |
| 2 | D | passive | Drain-source voltage is rated at 200 V (VDS) and the drain is the case/tab connection, with junction-to-case thermal resistance referenced to the drain. |
| 3 | S | passive | Source is the reference terminal for the gate-source voltage rating (±10 V) and the source-drain body diode, which is rated at 17 A continuous. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | D2PAK |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 200 | V | TC = 25 °C, unless otherwise noted | 1 | ||
| Gate-Source Voltage | VGS | -10 | 10 | V | 1 | ||
| Continuous Drain Current | ID | 17 | A | VGS at 5.0 V, TC = 25 °C | 1 | ||
| Continuous Drain Current | ID | 11 | A | VGS at 5.0 V, TC = 100 °C | 1 | ||
| Pulsed Drain Current | IDM | 68 | A | Repetitive rating; pulse width limited by maximum junction temperature | 1 | ||
| Linear Derating Factor | 1 | W/°C | 1 | ||||
| Linear Derating Factor (PCB mount) | 0.025 | W/°C | PCB mount, note e | 1 | |||
| Single Pulse Avalanche Energy | EAS | 580 | mJ | VDD = 50 V, starting TJ = 25 °C, L = 3.0 mH, Rg = 25 Ω, IAS = 17 A | 1 | ||
| Repetitive Avalanche Current | IAR | 10 | A | Repetitive rating; pulse width limited by maximum junction temperature | 1 | ||
| Repetitive Avalanche Energy | EAR | 13 | mJ | Repetitive rating; pulse width limited by maximum junction temperature | 1 | ||
| Maximum Power Dissipation | PD | 125 | W | TC = 25 °C | 1 | ||
| Maximum Power Dissipation (PCB mount) | PD | 3.1 | W | TA = 25 °C, PCB mount | 1 | ||
| Peak Diode Recovery dV/dt | dV/dt | 5 | V/ns | ISD ≤ 17 A, dI/dt ≤ 150 A/µs, VDD ≤ VDS, TJ ≤ 150 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Soldering Temperature | 300 | °C | for 10 s, 1.6 mm from case | 1 | |||
| Maximum Junction-to-Ambient | RthJA | 62 | °C/W | 2 | |||
| Maximum Junction-to-Ambient (PCB mount) | RthJA | 40 | °C/W | PCB mount, note a (1 in square PCB) | 2 | ||
| Maximum Junction-to-Case (Drain) | RthJC | 1 | °C/W | 2 | |||
| Drain-Source Breakdown Voltage | VDS | 200 | V | VGS = 0, ID = 250 µA | 2 | ||
| Gate-Source Threshold Voltage | VGS(th) | 1 | 2 | V | VDS = VGS, ID = 250 µA | 2 | |
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VGS = ±10 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 25 | µA | VDS = 200 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 250 | µA | VDS = 160 V, VGS = 0 V, TJ = 125 °C | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.18 | Ω | VGS = 5.0 V, ID = 10 A | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.27 | Ω | VGS = 4.0 V, ID = 8.5 A | 2 | ||
| Forward Transconductance | gfs | 16 | S | VDS = 50 V, ID = 10 A | 2 | ||
| Gate Input Resistance | Rg | 0.3 | 1.2 | Ω | f = 1 MHz, open drain | 2 | |
| Total Gate Charge | Qg | 66 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 | ||
| Gate-Source Charge | Qgs | 9 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 | ||
| Gate-Drain Charge | Qgd | 38 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 | ||
| Continuous Source-Drain Diode Current | IS | 17 | A | MOSFET symbol showing the integral reverse p-n junction diode | 2 | ||
| Pulsed Diode Forward Current | ISM | 68 | A | 2 | |||
| Body Diode Voltage | VSD | 2 | V | TJ = 25 °C, IS = 17 A, VGS = 0 V | 2 | ||
| Body Diode Reverse Recovery Time | trr | 310 | 470 | ns | TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µs | 2 | |
| Body Diode Reverse Recovery Charge | Qrr | 3.2 | 4.8 | µC | TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µs | 2 |
CAD (KiCad official)
- Symbol:
IRL640STRLPBF - Footprint:
Package_TO_SOT_SMD:TO-263-2 - 3D model: D2PAK (KiCad packages3D, STEP)
- 3D model files:
irl640strlpbf-etched.step/irl640strlpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);irl640strlpbf.step/irl640strlpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (9 pp, sha256
89c6e59bb7bb898b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IRL640STRLPBF
**Vishay Intertech** · MOSFETs · D2PAK
IRL640STRLPBF from Vishay Intertech, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate-source voltage is rated at ±10 V (VGS) in the absolute maximum ratings, and the gate input resistance is 0.3 to 1.2 Ω at 1 MHz. |
| 2 | D | passive | Drain-source voltage is rated at 200 V (VDS) and the drain is the case/tab connection, with junction-to-case thermal resistance referenced to the drain. |
| 3 | S | passive | Source is the reference terminal for the gate-source voltage rating (±10 V) and the source-drain body diode, which is rated at 17 A continuous. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | D2PAK |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | | | 200 | V | TC = 25 °C, unless otherwise noted | 1 |
| Gate-Source Voltage | VGS | -10 | | 10 | V | | 1 |
| Continuous Drain Current | ID | | | 17 | A | VGS at 5.0 V, TC = 25 °C | 1 |
| Continuous Drain Current | ID | | | 11 | A | VGS at 5.0 V, TC = 100 °C | 1 |
| Pulsed Drain Current | IDM | | | 68 | A | Repetitive rating; pulse width limited by maximum junction temperature | 1 |
| Linear Derating Factor | | | | 1 | W/°C | | 1 |
| Linear Derating Factor (PCB mount) | | | | 0.025 | W/°C | PCB mount, note e | 1 |
| Single Pulse Avalanche Energy | EAS | | | 580 | mJ | VDD = 50 V, starting TJ = 25 °C, L = 3.0 mH, Rg = 25 Ω, IAS = 17 A | 1 |
| Repetitive Avalanche Current | IAR | | | 10 | A | Repetitive rating; pulse width limited by maximum junction temperature | 1 |
| Repetitive Avalanche Energy | EAR | | | 13 | mJ | Repetitive rating; pulse width limited by maximum junction temperature | 1 |
| Maximum Power Dissipation | PD | | | 125 | W | TC = 25 °C | 1 |
| Maximum Power Dissipation (PCB mount) | PD | | | 3.1 | W | TA = 25 °C, PCB mount | 1 |
| Peak Diode Recovery dV/dt | dV/dt | | | 5 | V/ns | ISD ≤ 17 A, dI/dt ≤ 150 A/µs, VDD ≤ VDS, TJ ≤ 150 °C | 1 |
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Soldering Temperature | | | | 300 | °C | for 10 s, 1.6 mm from case | 1 |
| Maximum Junction-to-Ambient | RthJA | | | 62 | °C/W | | 2 |
| Maximum Junction-to-Ambient (PCB mount) | RthJA | | | 40 | °C/W | PCB mount, note a (1 in square PCB) | 2 |
| Maximum Junction-to-Case (Drain) | RthJC | | | 1 | °C/W | | 2 |
| Drain-Source Breakdown Voltage | VDS | 200 | | | V | VGS = 0, ID = 250 µA | 2 |
| Gate-Source Threshold Voltage | VGS(th) | 1 | | 2 | V | VDS = VGS, ID = 250 µA | 2 |
| Gate-Source Leakage | IGSS | -100 | | 100 | nA | VGS = ±10 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 25 | µA | VDS = 200 V, VGS = 0 V | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 250 | µA | VDS = 160 V, VGS = 0 V, TJ = 125 °C | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.18 | Ω | VGS = 5.0 V, ID = 10 A | 2 |
| Drain-Source On-State Resistance | RDS(on) | | | 0.27 | Ω | VGS = 4.0 V, ID = 8.5 A | 2 |
| Forward Transconductance | gfs | 16 | | | S | VDS = 50 V, ID = 10 A | 2 |
| Gate Input Resistance | Rg | 0.3 | | 1.2 | Ω | f = 1 MHz, open drain | 2 |
| Total Gate Charge | Qg | | | 66 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 |
| Gate-Source Charge | Qgs | | | 9 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 |
| Gate-Drain Charge | Qgd | | | 38 | nC | VGS = 5.0 V, ID = 17 A, VDS = 160 V | 2 |
| Continuous Source-Drain Diode Current | IS | | | 17 | A | MOSFET symbol showing the integral reverse p-n junction diode | 2 |
| Pulsed Diode Forward Current | ISM | | | 68 | A | | 2 |
| Body Diode Voltage | VSD | | | 2 | V | TJ = 25 °C, IS = 17 A, VGS = 0 V | 2 |
| Body Diode Reverse Recovery Time | trr | | 310 | 470 | ns | TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µs | 2 |
| Body Diode Reverse Recovery Charge | Qrr | | 3.2 | 4.8 | µC | TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µs | 2 |
## CAD (KiCad official)
- Symbol: `IRL640STRLPBF`
- Footprint: `Package_TO_SOT_SMD:TO-263-2`
- 3D model: D2PAK (KiCad packages3D, STEP)
- 3D model files: `irl640strlpbf-etched.step` / `irl640strlpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irl640strlpbf.step` / `irl640strlpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588949197777211392) (9 pp, sha256 `89c6e59bb7bb898b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/irl640strlpbf-datasheet.pdf)