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Contents

README

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IRL520NSTRLPBF

Infineon Technologies · MOSFETs · D2PAK

IRL520NSTRLPBF from Infineon Technologies, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Logic-level MOSFET control input; VGS(th) = 1.0-2.0 V, absolute max VGS = ±16 V. Drives the N-channel HEXFET on/off with respect to the Source.
2 D passive Drain. High-voltage power terminal (VDSS = 100 V, ID = 10 A at TC = 25 °C, RDS(on) = 0.18 Ω at VGS = 10 V). Internally connected to the metal mounting tab of the D²Pak.
3 S passive Source. Low-side power terminal of the N-channel MOSFET; return for the load current and reference for VGS. Body-diode anode is on Source (integral p-n junction diode: VSD ≈ 1.3 V, IS = 10 A).
TAB D passive Mounting tab, electrically connected to the Drain. Primary thermal path (RθJC = 3.1 °C/W); solder to a copper pad for heatsinking in surface-mount applications.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package D2PAK
Category Transistors/Thyristors
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • IRL520NSPbF
  • IRL520NSTRLPbF
  • IRL520NSTRRPbF
  • IRL520NLPbF

CAD (KiCad official)

  • Symbol: IRL520NSTRLPBF
  • Footprint: Package_TO_SOT_SMD:TO-263-2
  • 3D model: D2PAK (KiCad packages3D, STEP)
  • 3D model files: irl520nstrlpbf-etched.step / irl520nstrlpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irl520nstrlpbf.step / irl520nstrlpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (11 pp, sha256 92d07beefbfb4fa7, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF