component
IRF7204TR
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IRF7204TR
UMW · MOSFETs · SOP-8
IRF7204TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | SOURCE terminal of the P-channel MOSFET; pins 1, 2 and 3 are tied together as source, and the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 2 | S | passive | SOURCE terminal of the P-channel MOSFET (internally common with pins 1 and 3); the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 3 | S | passive | SOURCE terminal of the P-channel MOSFET (internally common with pins 1 and 2); the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 4 | G | input | GATE terminal of the P-channel MOSFET; gate-source voltage is rated ±20V (VGS) per the absolute maximum ratings. |
| 5 | D | passive | DRAIN terminal of the P-channel MOSFET; pins 5 through 8 are tied together as drain, with drain-source voltage rated -30V. |
| 6 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 7 and 8); drain-source voltage is rated -30V. |
| 7 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 6 and 8); drain-source voltage is rated -30V. |
| 8 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 6 and 7); drain-source voltage is rated -30V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -30 | V | VGS=0V, ID=-250μA | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS=-24V, VGS=0V | 3 | ||
| Gate-Source Leakage Current | IGSS | -100 | 100 | nA | VDS=±20V, VGS=0V | 3 | |
| Gate Threshold Voltage | VGS(th) | -1 | -2 | V | VDS=VGS, ID=-250μA | 3 | |
| Drain-Source On-State Resistance | RDS(ON) | 25 | mΩ | VGS=-10V, ID=-5.1A | 3 | ||
| Drain-Source On-State Resistance | RDS(ON) | 40 | mΩ | VGS=-4.5V, ID=-4.2A | 3 | ||
| Forward Transconductance | gFS | 20 | S | VDS=-15V, ID=-4.5A | 3 | ||
| Diode Forward Voltage | VSD | -1.2 | V | VGS=0V, ID=-5.1A | 3 | ||
| Drain-Source Voltage | VDS | -30 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Drain Current-Continuous | ID | -5.1 | A | 1 | |||
| Drain Current-Pulsed | IDM | -20 | A | Note 1 | 1 | ||
| Maximum Power Dissipation | PD | 2.5 | W | 1 | |||
| Operating Junction and Storage Temperature Range | TJ,TSTG | -55 | 150 | °C | 1 | ||
| Thermal Resistance, Junction-to-Ambient | RθJA | 50 | °C/W | Note 2 | 2 | ||
| Turn-on Delay Time | tD(on) | 7 | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 | ||
| Turn-on Rise Time | tr | 13 | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 | ||
| Turn-off Delay Time | tD(off) | 14 | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 | ||
| Turn-off Fall Time | tf | 9 | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 | ||
| Input Capacitance | Ciss | 520 | pF | VGS=0V, VDS=-15V, f=1MHz | 3 | ||
| Output Capacitance | Coss | 130 | pF | VGS=0V, VDS=-15V, f=1MHz | 3 | ||
| Reverse Transfer Capacitance | Crss | 70 | pF | VGS=0V, VDS=-15V, f=1MHz | 3 | ||
| Total Gate Charge | Qg | 11 | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 | ||
| Gate-Source Charge | Qgs | 2.2 | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 | ||
| Gate-Drain Charge | Qgd | 3 | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 |
CAD (KiCad official)
- Symbol:
IRF7204TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
irf7204tr-etched.step/irf7204tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);irf7204tr.step/irf7204tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (9 pp, sha256
a583f21e24f5e526, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IRF7204TR
**UMW** · MOSFETs · SOP-8
IRF7204TR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | SOURCE terminal of the P-channel MOSFET; pins 1, 2 and 3 are tied together as source, and the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 2 | S | passive | SOURCE terminal of the P-channel MOSFET (internally common with pins 1 and 3); the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 3 | S | passive | SOURCE terminal of the P-channel MOSFET (internally common with pins 1 and 2); the device is rated VDS = -30V with ID = -5.1A continuous at TA = 25°C. |
| 4 | G | input | GATE terminal of the P-channel MOSFET; gate-source voltage is rated ±20V (VGS) per the absolute maximum ratings. |
| 5 | D | passive | DRAIN terminal of the P-channel MOSFET; pins 5 through 8 are tied together as drain, with drain-source voltage rated -30V. |
| 6 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 7 and 8); drain-source voltage is rated -30V. |
| 7 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 6 and 8); drain-source voltage is rated -30V. |
| 8 | D | passive | DRAIN terminal of the P-channel MOSFET (internally common with pins 5, 6 and 7); drain-source voltage is rated -30V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -30 | | | V | VGS=0V, ID=-250μA | 3 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | µA | VDS=-24V, VGS=0V | 3 |
| Gate-Source Leakage Current | IGSS | -100 | | 100 | nA | VDS=±20V, VGS=0V | 3 |
| Gate Threshold Voltage | VGS(th) | -1 | | -2 | V | VDS=VGS, ID=-250μA | 3 |
| Drain-Source On-State Resistance | RDS(ON) | | | 25 | mΩ | VGS=-10V, ID=-5.1A | 3 |
| Drain-Source On-State Resistance | RDS(ON) | | | 40 | mΩ | VGS=-4.5V, ID=-4.2A | 3 |
| Forward Transconductance | gFS | 20 | | | S | VDS=-15V, ID=-4.5A | 3 |
| Diode Forward Voltage | VSD | | | -1.2 | V | VGS=0V, ID=-5.1A | 3 |
| Drain-Source Voltage | VDS | | | -30 | V | | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Drain Current-Continuous | ID | | | -5.1 | A | | 1 |
| Drain Current-Pulsed | IDM | | | -20 | A | Note 1 | 1 |
| Maximum Power Dissipation | PD | | | 2.5 | W | | 1 |
| Operating Junction and Storage Temperature Range | TJ,TSTG | -55 | | 150 | °C | | 1 |
| Thermal Resistance, Junction-to-Ambient | RθJA | | | 50 | °C/W | Note 2 | 2 |
| Turn-on Delay Time | tD(on) | | 7 | | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 |
| Turn-on Rise Time | tr | | 13 | | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 |
| Turn-off Delay Time | tD(off) | | 14 | | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 |
| Turn-off Fall Time | tf | | 9 | | ns | VDD=-15V, VGS=-10V, ID=-1A, RGEN=6Ω | 3 |
| Input Capacitance | Ciss | | 520 | | pF | VGS=0V, VDS=-15V, f=1MHz | 3 |
| Output Capacitance | Coss | | 130 | | pF | VGS=0V, VDS=-15V, f=1MHz | 3 |
| Reverse Transfer Capacitance | Crss | | 70 | | pF | VGS=0V, VDS=-15V, f=1MHz | 3 |
| Total Gate Charge | Qg | | 11 | | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 |
| Gate-Source Charge | Qgs | | 2.2 | | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 |
| Gate-Drain Charge | Qgd | | 3 | | nC | VDS=-15V, ID=-5.1A, VGS=-10V | 3 |
## CAD (KiCad official)
- Symbol: `IRF7204TR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `irf7204tr-etched.step` / `irf7204tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `irf7204tr.step` / `irf7204tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755879607646339072) (9 pp, sha256 `a583f21e24f5e526`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/irf7204tr-datasheet.pdf)