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IRF7104TRPBF

Infineon Technologies · MOSFETs · SO-8

IRF7104TRPBF from Infineon Technologies, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1 (VDSS -20V, ID -2.3A per device).
2 G1 input Gate of P-channel MOSFET 1, with VGS max ±12V and threshold -1.0V to -3.0V.
3 S2 passive Source of P-channel MOSFET 2 (VDSS -20V, ID -2.3A per device).
4 G2 input Gate of P-channel MOSFET 2, with VGS max ±12V and threshold -1.0V to -3.0V.
5 D2 passive Drain of P-channel MOSFET 2, tied to pin 6, with RDS(on) 0.25 ohm max at VGS -10V.
6 D2 passive Drain of P-channel MOSFET 2, tied to pin 5, with RDS(on) 0.25 ohm max at VGS -10V.
7 D1 passive Drain of P-channel MOSFET 1, tied to pin 8, with RDS(on) 0.25 ohm max at VGS -10V.
8 D1 passive Drain of P-channel MOSFET 1, tied to pin 7, with RDS(on) 0.25 ohm max at VGS -10V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SO-8
Category Transistors
Pins 8

CAD (KiCad official)

  • Symbol: IRF7104TRPBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: irf7104trpbf-etched.step / irf7104trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); irf7104trpbf.step / irf7104trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (10 pp, sha256 e62520da53b432d3, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF