component
IR3599MTRPBF
Public Made by Adomby adom
Infineon Technologies DC-DC Converters, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
| ir3599mtrpbf-etched.glb | 11d ago |
| ir3599mtrpbf-etched.step | 11d ago |
| ir3599mtrpbf-hero.glb | 11d ago |
| ir3599mtrpbf-hero.overlay.json | 11d ago |
| ir3599mtrpbf.glb | 11d ago |
| ir3599mtrpbf.kicad_mod | 11d ago |
| ir3599mtrpbf.kicad_sym | 11d ago |
| ir3599mtrpbf.lbr | 11d ago |
| ir3599mtrpbf.step | 11d ago |
| package.json | 11d ago |
| page.json | 11d ago |
| README.md | 11d ago |
IR3599MTRPBF
Infineon Technologies · DC-DC Converters · DFN-8-EP(2x2)
IR3599MTRPBF from Infineon Technologies, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PWM_IN | input | Control signal input to be connected to the controller PWM output; in Doubler mode it controls PWM1 and PWM2, and in Quad mode it controls PWM1 through PWM4. |
| 2 | V1p8 | power_out | 1.8V internal LDO output (1.67V to 1.93V at VCC=3.3V) that requires a 0.47uF high-quality low-ESR ceramic capacitor to GND. |
| 3 | VCC | power_in | Connect to a +3.3V bias supply (VCC range +2.85V to +3.6V) with a 0.1uF high-quality low-ESR ceramic capacitor to GND. |
| 4 | FUNCTION | input | Tie to GND or VCC to select Doubler or Quad phase mode; the level is latched at power-up and cannot be changed after initial power-up. |
| 5 | PWM4 | output | Channel 4 PWM signal to the power stage, which goes to high impedance when PWM_IN is tri-stated. |
| 6 | PWM3 | output | Channel 3 PWM signal to the power stage, which goes to high impedance when PWM_IN is tri-stated. |
| 7 | PWM2 | output | Channel 2 PWM signal to the power stage, which goes to high impedance when PWM_IN is tri-stated. |
| 8 | PWM1 | output | Channel 1 PWM signal to the power stage, which goes to high impedance when PWM_IN is tri-stated. |
| 9 | GND | power_in | Bias and reference ground (exposed pad); all signals are referenced to this node. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | DFN-8-EP(2x2) |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.85 | 3.3 | 3.6 | V | 7 | |
| LDO Output Voltage | VLDO | 1.67 | 1.8 | 1.93 | V | VCC=3.3V | 7 |
| PWM Input Tri-State Float Voltage | VPWM_IN | 1.4 | 1.5 | 1.62 | V | PWM_IN = floating | 8 |
| PWM Output High Threshold (IR3599) | VOH(PWM) | 2.85 | V | 8 | |||
| PWM Output Low Threshold (IR3599) | VOL(PWM) | 0.4 | V | 8 | |||
| VCC Supply Voltage Range (recommended) | VCC | 2.85 | 3.6 | V | 7 | ||
| Recommended Operating Ambient Temperature Range | -40 | 85 | °C | 7 | |||
| Maximum Operating Junction Temperature | 125 | °C | 7 | ||||
| PWM Output Frequency Range | 200 | 800 | kHz | 7 | |||
| VCC Absolute Maximum | VCC | -0.3 | 4 | V | 6 | ||
| V1P8 Absolute Maximum | V1P8 | -0.3 | 2.2 | V | 6 | ||
| PWM_IN, FUNCTION Absolute Voltage | -0.3 | V | max VCC +0.3V | 6 | |||
| PWMx Absolute Voltage | -0.3 | V | max VCC +0.3V | 6 | |||
| ESD HBM | 2 | kV | HBM Class 1-C | 6 | |||
| Maximum Junction Temperature | 150 | °C | 6 | ||||
| Maximum Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Maximum Lead Temperature (Soldering) | 300 | °C | 10s | 6 | |||
| Thermal Resistance (ΘJC) | ΘJC | 8.9 | °C/W | 6 | |||
| Thermal Resistance (ΘJA) | ΘJA | 73.2 | °C/W | Note 1: measured on high effective thermal conductivity test board in free air | 6 |
CAD (KiCad official)
- Symbol:
IR3599MTRPBF - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
ir3599mtrpbf-etched.step/ir3599mtrpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ir3599mtrpbf.step/ir3599mtrpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (18 pp, sha256
9186728cf7649203, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).