component
IR3537MTRPBF
Public Made by Adomby adom
Infineon Technologies Gate Drive ICs, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIR3537MTRPBF
Infineon Technologies · Gate Drive ICs · DFN-10-EP(3x3)
IR3537MTRPBF from Infineon Technologies, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Floating bootstrap supply pin for the upper gate drive, with a bootstrap capacitor connected between this pin and the SWITCH pin. |
| 2 | HVCC | power_in | Supply for the high-side gate drive, connected to VCC (+12V) or a separate supply between 4.5V and 13.2V, and to the anode of the internal bootstrap diode, with a low ESR ceramic capacitor to GND. |
| 3 | PWM | input | Control input for the driver accepting a 1.8V or 3.3V PWM signal from the controller, which can enter three distinct states during operation. |
| 4 | VCC | power_in | Connected to a +12V bias supply, with a high quality low ESR ceramic capacitor from this pin to GND. |
| 5 | LVCC | power_in | Low-side gate drive supply, connected to VCC (+12V) or a separate supply between 4.5V and 13.2V, which must always be less than or equal to VCC+0.7Vdc. |
| 6 | LO_GATE | output | Lower gate drive output connected to the gate of the low-side power N-channel MOSFET. |
| 7 | GND | power_in | Bias and reference ground to which all signals are referenced, and the power ground return of the driver. |
| 8 | MODE | input | Selects the PWM mode: floating configures IR Active Tri-Level operation with 1.8V PWM, and connecting to ground configures generic active tri-state operation with 3.3V PWM. |
| 9 | SWITCH | passive | Connected to the source of the upper MOSFET and the drain of the lower MOSFET, providing the return path for the upper gate drive. |
| 10 | HI_GATE | output | Upper gate drive output connected to the gate of the high-side power N-channel MOSFET. |
| 11 | GND | power_in | Exposed thermal pad serving as bias and reference ground for all signals and as the power ground return of the driver. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | DFN-10-EP(3x3) |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| BOOT pin voltage, reference to GND | 35 | V | Reference to GND | 5 | |||
| BOOT pin voltage, reference to SWITCH | 15 | V | Reference to SWITCH | 5 | |||
| PWM pin voltage | PWM | 7 | V | 5 | |||
| VCC, HVCC supply voltage | VCC, HVCC | 15 | V | 5 | |||
| LVCC supply voltage | LVCC | 15 | V | VCC+0.7Vdc to a maximum of +15.0V | 5 | ||
| LO_GATE voltage, DC | LO_GATE | -0.3 | 0.3 | V | DC; max is 0.3V above VCC | 5 | |
| LO_GATE voltage, <200 ns | LO_GATE | -2 | 0.3 | V | <200 ns; max is 0.3V above VCC | 5 | |
| SWITCH voltage, DC | SWITCH | -0.3 | 15 | V | DC | 5 | |
| SWITCH voltage, <20 ns | SWITCH | 25 | V | <20 ns | 5 | ||
| SWITCH voltage, <5 ns | SWITCH | -10 | V | <5 ns | 5 | ||
| SWITCH voltage, <20 ns (negative) | SWITCH | -4 | V | <20 ns | 5 | ||
| SWITCH voltage, <200 ns (negative) | SWITCH | -2 | V | <200 ns | 5 | ||
| HI_GATE voltage, DC | HI_GATE | -0.3 | 0.3 | V | DC; min relative to SWITCH, max 0.3V above VBOOT | 5 | |
| HI_GATE voltage, <200 ns | HI_GATE | -2 | 0.3 | V | <200 ns; min relative to SWITCH, max 0.3V above VBOOT | 5 | |
| MODE pin voltage | MODE | -0.3 | 15 | V | 5 | ||
| ESD, Charged Device Model | -1000 | 1000 | V | JESD22-C101-C, passes +/-1000V | 5 | ||
| Recommended operating ambient temperature | 0 | 85 | °C | 6 | |||
| Recommended operating junction temperature | 125 | °C | 6 | ||||
| Recommended LVCC & HVCC range | LVCC, HVCC | 4.5 | 13.2 | V | LVCC must be ≤ VCC+0.7Vdc | 6 | |
| Recommended supply voltage tolerance | VCC | -10 | 10 | % | +12V ± 10% | 6 | |
| Recommended supply voltage | VCC | 12 | V | +12V ± 10% | 6 | ||
| Maximum storage temperature range | -65 | 150 | °C | 5 | |||
| Maximum operating junction temperature | 150 | °C | 5 | ||||
| Maximum lead temperature (soldering) | 300 | °C | Soldering 10 s | 5 | |||
| Thermal resistance, junction-to-case (θJC) | θJC | 3 | °C/W | 5 | |||
| Thermal resistance, junction-to-ambient (θJA) | θJA | 45 | °C/W | Note 1: measured with component mounted on high effective thermal conductivity test board in free air | 5 |
CAD (KiCad official)
- Symbol:
IR3537MTRPBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ir3537mtrpbf-etched.step/ir3537mtrpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ir3537mtrpbf.step/ir3537mtrpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (15 pp, sha256
a7a0c5ee65dc2722, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).