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IR35204MTRPBF

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Infineon Technologies DC-DC Converters, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsir35204mtrpbffactory-2.0.0extractor-text

Changed since verified IR35204MTRPBF

by Ray · last 2 Nov 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: IR35204MTRPBF · QFN-40-EP(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 61-page datasheet
  • ✓distributor: lcsc C537648, digikey 448-IR35204MTRPBFTR-ND, mouser 942-IR35204MTRPBF
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rywgs4v2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
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Verified files! ir35204mtrpbf.kicad_sym✓ ir35204mtrpbf.kicad_mod✓ ir35204mtrpbf.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers ir35204mtrpbf: symbol repaired (body fitted to the names) · Ray 2d ago
ir35204mtrpbf-etched.glb Publish 0.1.0 · Ray 4d ago
ir35204mtrpbf-etched.step ir35204mtrpbf: factory component page (tier=mfr) · Ray 4d ago
ir35204mtrpbf-hero.glb ir35204mtrpbf: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
ir35204mtrpbf-hero.overlay.json Publish 0.1.0 · Ray 4d ago
ir35204mtrpbf.glb Publish 0.1.0 · Ray 4d ago
ir35204mtrpbf.kicad_mod Publish 0.1.0 · Ray 4d ago
ir35204mtrpbf.kicad_sym ir35204mtrpbf: symbol repaired (body fitted to the names) · Ray 2d ago
ir35204mtrpbf.lbr ir35204mtrpbf: symbol repaired (body fitted to the names) · Ray 2d ago
ir35204mtrpbf.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 41 pins · Ray 4d ago

IR35204MTRPBF

Infineon Technologies · DC-DC Converters · QFN-40-EP(5x5)

IR35204MTRPBF from Infineon Technologies, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RCSM output Resistor current sense minus for Loop 1, connected to an external network that sets load line slope, bandwidth and temperature compensation.
2 VRDY2 output Open-drain Loop 2 VR ready output that asserts high after soft-start to the Loop 2 boot voltage and requires a pull-up to an external voltage through a resistor.
3 VSEN input Loop 1 voltage sense input connected directly to the VR output at the load and routed differentially with VRTN.
4 VRTN input Loop 1 voltage sense return input connected directly to Loop 1 ground at the load and routed differentially with VSEN.
5 I_IN input Input current signal ranging from 0 to 1 Vdc that indicates a maximum input current of 62.5A.
6 TSEN1 input Loop 1 temperature sense input for an NTC network or IR PowIRstage temperature output, which must be scaled to 4.88 mV per degC with a 0.365 Vdc offset when used with the PowIRstage.
7 CFILT output Decoupling pin for the internal 1.8V supply, which requires an external capacitor on this pin.
8 VRDY1 output Open-drain Loop 1 VR ready output that asserts high after soft-start to the Loop 1 boot voltage and requires a pull-up to an external voltage through a resistor.
9 EN_L2/CAT_FLT/PWROK input Multi-function pin: Loop 2 enable input, AMD PWROK input (low returns to boot voltage, high selects SVI bus), or CAT_FLT output driven to VCC under output OVP, NVM CRC error or TSEN fault.
10 VINSEN input Input supply voltage sense used to detect and measure a valid VR input supply, typically 4.5V to 13.2V.
11 SV_ADDR/VDDIO input Serial VID address pin where a resistor to ground sets the NVM SVID address offset and needs a 0.01uF filter capacitor, or AMD VDDIO input that sets the voltage to which SVT and SVD acknowledge are driven high.
12 SV_ALERT#/SVT output Intel SVID ALERT# output pulled low to alert the CPU of VR status and requiring a pull-up, or AMD SVI telemetry and VOTF output.
13 SV_CLK input Serial VID clock input driven by the CPU master.
14 SV_DIO bidirectional Bidirectional serial VID data line over which the CPU master issues commands and receives data from slaves.
15 VRHOT_ICRIT# output Active-low alert output that asserts when temperature or average load current exceeds user-definable thresholds and requires a pull-up to an external voltage.
16 EN input VR enable input that powers the regulator when Vin and Vcc are present, has no internal pull-up, and must be pulled high or low rather than left floating.
17 ADDR_PROT bidirectional Bus address and I2C protection pin where a resistor to ground sets the NVM I2C address offset, then becomes a logic input that enables or disables I2C communication, with a 0.01uF filter capacitor required.
18 SM_ALERT# output Active-low SMBus/PMBus alert line indicating a change in regulator status, requires a pull-up, and must be grounded if not used.
19 SM_DIO bidirectional Bidirectional I2C/SMBus/PMBus serial data line that must be grounded if not used.
20 SM_CLK input I2C/SMBus/PMBus clock input rated to 1 MHz that must be grounded if not used.
21 PIN_ALERT# output Active-low alert output that asserts when input power exceeds a user-defined threshold and requires a pull-up to an external voltage.
22 TSEN2/VAUXSEN input Loop 2 temperature sense input for an NTC network or PowIRstage output that should float if not used, shared with an auxiliary voltage sense input that monitors a supply for Vcc and driver operation and should float if not used.
23 PWM1 output Phase 1 PWM output connected to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active.
24 PWM2 output Phase 2 PWM output connected to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active.
25 PWM3 output Phase 3 PWM output connected to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active.
26 PWM1_L2 output Loop 2 phase 1 PWM output connected to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active, and floated if not used.
27 VRTN_L2 input Loop 2 voltage sense return input connected to Loop 2 ground at the load and routed differentially with VSEN_L2, and connected to GND if not used.
28 VSEN_L2 input Loop 2 voltage sense input connected directly to the Loop 2 VR output at the load and routed differentially with VRTN_L2, and connected to GND if not used.
29 VCC power_in Input supply pin that powers the device from a 3.3V supply.
30 RCSM_L2 output Loop 2 resistor current sense minus network that sets load line slope, bandwidth and temperature compensation, connected to pin 31 with a 10K resistor if not used.
31 RCSP_L2 output Loop 2 resistor current sense positive network that sets load line slope, bandwidth and temperature compensation, connected to pin 30 with a 10K resistor if not used.
32 ISEN1_L2 input Loop 2 phase 1 positive current sense input, connected to GND if not used.
33 IRTN1_L2 input Loop 2 phase 1 current sense return input, connected to GND if not used.
34 ISEN3 input Phase 3 positive current sense input, connected to GND if not used.
35 IRTN3 input Phase 3 current sense return input, connected to GND if not used.
36 ISEN2 input Phase 2 positive current sense input, connected to GND if not used.
37 IRTN2 input Phase 2 current sense return input, connected to GND if not used.
38 ISEN1 input Phase 1 positive current sense input, connected to GND if not used.
39 IRTN1 input Phase 1 current sense return input, connected to GND if not used.
40 RCSP output Loop 1 resistor current sense positive network that sets load line slope, bandwidth and temperature compensation.
41 GND power_in Ground reference for the IC; the large metal pad on the bottom must be connected to ground.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package QFN-40-EP(5x5)
Category Power Management ICs
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Recommended Operating Ambient Temperature Range -40 85 °C 8
Supply Voltage Range 2.9 3.63 V 8
Supply Voltage (VCC) VCC -0.3 4 V GND-0.3V to 4.0V 7
RCSPx, RCSMx 0 2.2 V 7
VSEN, VRTN, ISENx, IRTNx -0.2 V max VCC + 0.3V 7
CFILT, VINSEN, I_IN -0.2 2.2 V 7
TSENx -0.3 V max VCC 7
SV_CLK, SV_DIO, SV_ALERT#, SV_ADDR -0.3 V max VCC 7
VRDYx, ENx, ADDR_PROT, VRHOT_ICRIT#, PIN_ALERT# -0.3 V max VCC 7
PWMx -0.3 4.1 V 7
SM_DIO, SM_CLK, SM_ALERT# -0.3 5.5 V 7
ESD Rating Human Body Model 2000 V Human Body Model 7
ESD Rating Machine Model 200 V Machine Model 7
ESD Rating Charge Device Model 1000 V Charge Device Model 7
Maximum Operating Junction Temperature -40 125 °C 7
Maximum Storage Temperature Range -65 150 °C 7
Maximum Lead Temperature (Soldering 10s) 300 °C soldering 10s 7
3.3V UVLO Turn-on Threshold 2.8 2.9 V 8
3.3V UVLO Turn-off Threshold 2.6 2.7 V 8
Input Impedance (VINSEN) 1 MΩ 8
Input Range V12 0 0.857 1.1 V With 14:1 divider 8
UVLO Turn-on Programmable Range 4.5 13.2 V With 14:1 divider 8
UVLO Turn-off Programmable Range 4.5 13.2 V With 14:1 divider 8
OVP Threshold 14.3 14.6 14.9 V if enabled 8
UVLO Turn-on Threshold (VAUXSEN) VAUXSEN_on 0.642 0.664 0.686 mV 8
UVLO Turn-off Threshold (VAUXSEN) VAUXSEN_off 0.564 0.586 0.608 mV 8
System Accuracy (0 to 85°C ambient) -1.1 1.1 %VID VID = 2.005-3.04V 8
System Accuracy (0 to 85°C ambient) -0.5 0.5 %VID VID = 1.0V-2.0V 8
System Accuracy (0 to 85°C ambient) -5 5 mV VID = 0.8, 0.995V 8
System Accuracy (0 to 85°C ambient) -8 8 mV VID = 0.25 -0.795V 8
System Accuracy (-40°C to 125°C junction) -1.65 1.65 %VID VID = 2.005-3.04V 8
System Accuracy (-40°C to 125°C junction) -0.75 0.75 %VID VID = 1.0V-2.0V 8
System Accuracy (-40°C to 125°C junction) -7.5 7.5 mV VID = 0.8, 0.995V 8
System Accuracy (-40°C to 125°C junction) -12 12 mV VID = 0.25 -0.795V 8
Frequency Accuracy -2.5 2.5 % 0°C to 85°C 8
Frequency Accuracy -5 5 % -40°C to 125°C 8
PWM Frequency Range 194 2000 kHz 8
NTC Output Current TSEN_NTC 96 100 104 µA For TSEN = 0 to 1.2V 9
NTC Accuracy 96 104 °C at 100°C (ideal NTC) 9
Digital Inputs Low Vth Type 1 Input High Voltage 0.7 V EN(_L2) (Intel), VRHOT_ICRIT# (during PoR) 9
Digital Inputs Low Vth Type 1 Input Low Voltage 0.35 V EN(_L2) (Intel), VRHOT_ICRIT# (during PoR) 9
Digital Inputs Low Vth Type 1 Input Leakage Current -5 5 µA Vpad = 0 to 2V 9
Digital Inputs Low Vth Type 2 Input High Voltage 0.65 V SV_CLK, SV_DIO 9
Digital Inputs Low Vth Type 2 Input Low Voltage 0.45 V SV_CLK, SV_DIO 9
Digital Inputs Low Vth Type 2 Input Leakage Current -1 1 µA Vpad = 0 to 2V 9
Digital Inputs LVTTL Input High Voltage 2.1 V SM_DIO, SM_CLK, EN(_L2), ADDR_PROT 9
Digital Inputs LVTTL Input Low Voltage 0.8 V SM_DIO, SM_CLK, EN(_L2), ADDR_PROT 9
Digital Inputs LVTTL Input Leakage -1 1 µA Vpad = 0 to 3.6V 9
VSEN Input Current -25 100 µA VCPU = 0.5V to 3.04V 9
Differential Input Voltage Range 0 3.04 V VRTN = ±100mV 9
VRTN Input CM Voltage -100 100 mV 9
Remote Current Sense Inputs ISENx/IRTNx Voltage Range -0.1 V max VCC - 0.65 9
Input Current Sense Input I_IN Voltage Range 0 1.25 V 9
Analog Address/Level Inputs ADDR_PROT,SV_ADDR Output Current 96 100 104 µA Vpad = 0 to 1.2V 9
Fast OCP Range (per phase) 0 62 A 12
OCP System Accuracy -2 2 % System excluding DCR/sense resistor 12
VR_HOT Range 64 127 °C 12
OTP Range (added to VR_HOT level) 0 31 °C 12
Thermal Resistance θJA θJA 29 °C/W measured with component mounted on high effective thermal conductivity test board in free air 7
Thermal Resistance θJC θJC 3 °C/W 7

CAD (KiCad official)

  • Symbol: IR35204MTRPBF
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ir35204mtrpbf-etched.step / ir35204mtrpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ir35204mtrpbf.step / ir35204mtrpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (61 pp, sha256 38fd0f28a1ca0bcc, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF