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IR35201MTRPBF
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Infineon Technologies DC-DC Converters, QFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IR35201MTRPBF
Infineon Technologies · DC-DC Converters · QFN-56-EP(7x7)
IR35201MTRPBF from Infineon Technologies, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ISEN6 | input | Phase 6 sensed current input (+); short to GND if not used. |
| 2 | RCSP | output | Resistor Current Sense Positive for Loop 1, connected to an external network that sets load line slope, bandwidth and temperature compensation. |
| 3 | RCSM | output | Resistor Current Sense Minus for Loop 1, connected to an external network that sets load line slope, bandwidth and temperature compensation. |
| 4 | VRDY2 | output | Open-drain Voltage Regulator Ready output for Loop 2 that asserts high when soft-start to the Loop 2 boot voltage is complete; pull up to an external voltage through a resistor. |
| 5 | VSEN | input | Loop 1 voltage sense input connected at the load, to be routed differentially with VRTN. |
| 6 | VRTN | input | Loop 1 voltage sense return input connected to Loop 1 ground at the load, to be routed differentially with VSEN. |
| 7 | NC | unconnected | Do not connect. |
| 8 | I_IN | input | Input current signal ranging from 0 to 1.25Vdc, indicating a maximum input current of 62.5 A. |
| 9 | TSEN1 | input | Loop 1 temperature sense input for an NTC network or IR PowIRstage temperature output, used for VRHOT and OTP; PowIRstage output must be scaled to 4.88mV/°C with a 0.365Vdc offset. |
| 10 | CFILT | output | 1.8V decoupling pin for the internal 1.8V supply, requiring a 1µF capacitor. |
| 11 | VRDY1 | output | Open-drain Voltage Regulator Ready output for Loop 1 that asserts high when soft-start to the Loop 1 boot voltage is complete; pull up to an external voltage through a resistor. |
| 12 | EN_L2/PWROK/CAT_FLT | input | Multiplexed pin: Enable input for Loop 2, PWROK power-OK input (AMD) that returns to Boot voltage when low and uses the SVI bus when high, or CAT_FLT CMOS output driven to VCC on output OVP, NVM CRC error or TSEN fault. |
| 13 | NC | unconnected | Do not connect. |
| 14 | VINSEN | input | Input supply voltage sense used to detect and measure a valid VR input supply, typically 4.5V-13.2V. |
| 15 | NC | unconnected | Do not connect. |
| 16 | SV_ADDR/VDDIO | input | Multiplexed pin: SV_ADDR serial VID address input where a resistor to ground sets the NVM SVID address offset and requires 0.01µF to ground, or VDDIO (AMD) supply to which the SVT line and SVD Acknowledge are driven high. |
| 17 | SV_ALERT#/SVT | output | Multiplexed pin: SV_ALERT# open output pulled low to alert the CPU of IMVP8/VR12/VR12.5 status changes (Intel), or SVT telemetry and VOTF information output (AMD); pull up through a resistor. |
| 18 | SV_CLK | input | Serial VID clock input driven by the CPU master. |
| 19 | SV_DIO | bidirectional | Serial VID bi-directional data line over which the CPU master issues commands and receives data from the controller. |
| 20 | VRHOT_ICRIT# | output | Active-low alert output that asserts when temperature or average load current exceeds user-definable thresholds; pull up to an external voltage through a resistor. |
| 21 | EN | input | VR enable input that powers the regulator when Vin and Vcc are present; it is not pulled up internally, polarity is bit-settable, and it cannot be left floating. |
| 22 | ADDR_PROT | bidirectional | Address resistor offset and I2C bus protection pin; a resistor to ground sets the NVM I2C address offset, then it acts as a logic input to enable or disable I2C communication, requiring 0.01µF to ground for noise filtering. |
| 23 | SM_ALERT# | output | Active-low SMBus/PMBus alert output indicating regulator status change; requires a pull-up, or ground if not used. |
| 24 | SM_DIO | bidirectional | I2C/SMBus/PMBus bi-directional serial data line; ground if not used. |
| 25 | SM_CLK | input | I2C/SMBus/PMBus clock input rated to 1 MHz; ground if not used. |
| 26 | PIN_ALERT# | output | Active-low alert output that asserts when input power exceeds a user-defined threshold; pull up to an external voltage through a resistor. |
| 27 | TSEN2/VAUXSEN | output | Multiplexed pin: Loop 2 temperature sense input for an NTC network or IR PowIRstage temperature output for VRHOT (float if not used), or auxiliary voltage sense input monitoring an additional supply for Vcc and driver operation (float if not used). |
| 28 | PWM1 | output | Phase 1 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 29 | PWM2 | output | Phase 2 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 30 | PWM3 | output | Phase 3 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 31 | PWM4 | output | Phase 4 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 32 | PWM5 | output | Phase 5 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 33 | PWM6 | output | Phase 6 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 34 | PWM7/PWM2_L2 | output | Multiplexed pin: Phase 7 PWM output, or Loop 2 Phase 2 PWM output, each connected to an external MOSFET gate driver input, high-impedance until ENABLE goes active; float if not used. |
| 35 | PWM8/PWM1_L2 | output | Multiplexed pin: Phase 8 PWM output, or Loop 2 Phase 1 PWM output, each connected to an external MOSFET gate driver input, high-impedance until ENABLE goes active; float if not used. |
| 36 | VRTN_L2 | input | Loop 2 voltage sense return input connected to Loop 2 ground at the load, to be routed differentially with VSEN_L2; short to GND if not used. |
| 37 | VSEN_L2 | input | Loop 2 voltage sense input connected to the Loop 2 VR output at the load, to be routed differentially with VRTN_L2; short to GND if not used. |
| 38 | VCC | power_in | 3.3V input supply voltage to power the device (absolute maximum 4.0V). |
| 39 | RCSM_L2 | input | Loop 2 resistor current sense minus connected to an external load-line/bandwidth/temperature network; connect to RCSP_L2 with 10kΩ if not used. |
| 40 | RCSP_L2 | input | Loop 2 resistor current sense positive connected to an external network that sets load-line slope, bandwidth and temperature compensation. |
| 41 | NC | unconnected | Do not connect. |
| 42 | ISEN1_L2/ISEN8 | input | Multiplexed pin: Loop 2 Phase 1 sensed current input (+), or Phase 8 sensed current input (+); short to GND if not used. |
| 43 | IRTN1_L2/IRTN8 | input | Multiplexed pin: Loop 2 Phase 1 sensed current return input (-), or Phase 8 sensed current return input (-); short to GND if not used. |
| 44 | ISEN2_L2/ISEN7 | input | Multiplexed pin: Loop 2 Phase 2 sensed current input (+), or Phase 7 sensed current input (+); short to GND if not used. |
| 45 | IRTN2_L2/IRTN7 | input | Multiplexed pin: Loop 2 Phase 2 sensed current return input (-), or Phase 7 sensed current return input (-); short to GND if not used. |
| 46 | ISEN5 | input | Phase 5 sensed current input (+); short to GND if not used. |
| 47 | IRTN5 | input | Phase 5 sensed current return input (-); short to GND if not used. |
| 48 | ISEN4 | input | Phase 4 sensed current input (+); short to GND if not used. |
| 49 | IRTN4 | input | Phase 4 sensed current return input (-); short to GND if not used. |
| 50 | ISEN3 | input | Phase 3 sensed current input (+); short to GND if not used. |
| 51 | IRTN3 | input | Phase 3 sensed current return input (-); short to GND if not used. |
| 52 | ISEN2 | input | Phase 2 sensed current input (+); short to GND if not used. |
| 53 | IRTN2 | input | Phase 2 sensed current return input (-); short to GND if not used. |
| 54 | ISEN1 | input | Phase 1 sensed current input (+); short to GND if not used. |
| 55 | IRTN1 | input | Phase 1 sensed current return input (-); short to GND if not used. |
| 56 | IRTN6 | input | Phase 6 sensed current return input (-); short to GND if not used. |
| 57 | GND | power_in | Ground reference for the IC; the large metal pad on the bottom must be connected to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | QFN-56-EP(7x7) |
| Category | Power Management ICs |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC) | VCC | -0.3 | 4 | V | Referenced to GND; min printed as GND-0.3V | 8 | |
| RCSPx, RCSMx voltage | 0 | 2.2 | V | 8 | |||
| VSEN, VRTN, ISENx, IRTNx voltage | -0.2 | V | Max printed as VCC + 0.3V | 8 | |||
| CFILT, VINSEN, I_IN voltage | -0.2 | 2.2 | V | 8 | |||
| TSENx voltage | -0.3 | V | Max printed as VCC | 8 | |||
| SV_CLK, SV_DIO, SV_ALERT#, SV_ADDR voltage | -0.3 | V | Max printed as VCC | 8 | |||
| VRDYx, ENx, ADDR_PROT, VRHOT_ICRIT#, PIN_ALERT# voltage | -0.3 | V | Max printed as VCC | 8 | |||
| PWMx voltage | -0.3 | 4.1 | V | 8 | |||
| SM_DIO, SM_CLK, SM_ALERT# voltage | -0.3 | 5.5 | V | 8 | |||
| Maximum Operating Junction Temperature | -40 | 125 | °C | 8 | |||
| Maximum Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Recommended Operating Ambient Temperature Range | -40 | 85 | °C | 9 | |||
| Supply Voltage Range | 2.9 | 3.63 | V | 9 | |||
| Supply Voltage | Vcc | 2.9 | 3.3 | 3.63 | V | 9 | |
| 3.3V UVLO Turn-on Threshold | 2.8 | 2.9 | V | 9 | |||
| 3.3V UVLO Turn-off Threshold | 2.6 | 2.7 | V | 9 | |||
| Input Impedance (VINSEN) | 1 | MΩ | 9 | ||||
| Input Range V12 | 0 | 0.857 | 1.1 | V | With 14:1 divider | 9 | |
| UVLO Turn-on Programmable Range | 4.5 | 13.2 | V | With 14:1 divider | 9 | ||
| UVLO Turn-off Programmable Range | 4.5 | 13.2 | V | With 14:1 divider | 9 | ||
| OVP Threshold (if enabled) | 14.3 | 14.6 | 14.9 | V | If enabled | 9 | |
| AUX Voltage UVLO Turn-on Threshold | VAUXSEN_on | 0.642 | 0.664 | 0.686 | mV | 9 | |
| AUX Voltage UVLO Turn-off Threshold | VAUXSEN_off | 0.564 | 0.586 | 0.608 | mV | 9 | |
| System Accuracy | -1.1 | 1.1 | %VID | VID = 2.005-3.04V; 0 to 85°C ambient | 9 | ||
| System Accuracy | -0.5 | 0.5 | %VID | VID = 1.0V-2.0V; 0 to 85°C ambient | 9 | ||
| System Accuracy | -5 | 5 | mV | VID = 0.8-0.995V; 0 to 85°C ambient | 9 | ||
| System Accuracy | -8 | 8 | mV | VID = 0.25-0.795V; 0 to 85°C ambient | 9 | ||
| System Accuracy | -1.65 | 1.65 | %VID | VID = 2.005-3.04V; -40°C to 125°C junction | 9 | ||
| System Accuracy | -0.75 | 0.75 | %VID | VID = 1.0V-2.0V; -40°C to 125°C junction | 9 | ||
| System Accuracy | -7.5 | 7.5 | mV | VID = 0.8-0.995V; -40°C to 125°C junction | 9 | ||
| System Accuracy | -12 | 12 | mV | VID = 0.25-0.795V; -40°C to 125°C junction | 9 | ||
| Frequency Accuracy | -2.5 | 2.5 | % | 0°C to 85°C | 9 | ||
| Frequency Accuracy | -5 | 5 | % | -40°C to 125°C | 9 | ||
| PWM Frequency Range | 194 | 2000 | kHz | 9 | |||
| NTC Output Current | TSEN_NTC | 96 | 100 | 104 | µA | For TSEN = 0 to 1.2V | 10 |
| NTC Temperature Sense Accuracy | 96 | 104 | °C | At 100°C (ideal NTC) | 10 | ||
| Digital Input High Voltage (Type 1) | 0.7 | V | EN(_L2), VRHOT_ICRIT# (during PoR) | 10 | |||
| Digital Input Low Voltage (Type 1) | 0.35 | V | EN(_L2), VRHOT_ICRIT# (during PoR) | 10 | |||
| Digital Input Leakage Current (Type 1) | -5 | 5 | µA | Vpad = 0 to 2V | 10 | ||
| Digital Input High Voltage (Type 2) | 0.65 | V | SV_CLK, SV_DIO | 10 | |||
| Digital Input Low Voltage (Type 2) | 0.45 | V | SV_CLK, SV_DIO | 10 | |||
| Digital Input Leakage Current (Type 2) | -1 | 1 | µA | Vpad = 0 to 2V | 10 | ||
| LVTTL Input High Voltage | 2.1 | V | SM_DIO, SM_CLK, EN(_L2), ADDR_PROT | 10 | |||
| LVTTL Input Low Voltage | 0.8 | V | SM_DIO, SM_CLK, EN(_L2), ADDR_PROT | 10 | |||
| LVTTL Input Leakage | -1 | 1 | µA | Vpad = 0 to 3.6V | 10 | ||
| VSEN Input Current | -25 | 100 | µA | VCPU = 0.5V to 3.04V | 10 | ||
| Differential Input Voltage Range | 0 | 3.04 | V | VRTN = ±100mV | 10 | ||
| Remote Current Sense Input Voltage Range (ISENx/IRTNx) | -0.1 | V | Max printed as VCC - 0.65 | 10 | |||
| Analog Address/Level Inputs Output Current | 96 | 100 | 104 | µA | Vpad = 0 to 1.2V | 10 | |
| CAT_FLT Output Low Voltage | 0.4 | V | Iol = 20mA | 10 | |||
| Open-Drain Output Low Voltage | 0.3 | V | 4mA drive | 10 | |||
| OVP Operating Threshold (programmable) | 50 | 400 | mV | Relative to VID | 12 | ||
| Output UVP Threshold (programmable) | 50 | 400 | mV | Relative to VID | 12 | ||
| Fast OCP Range (per phase) | 0 | 62 | A | 12 | |||
| OCP System Accuracy | -2 | 2 | % | System excluding DCR/sense resistor | 12 | ||
| VR_HOT Range | 64 | 127 | °C | 12 | |||
| OTP Range (added to VR_HOT level) | 0 | 31 | °C | 12 | |||
| Temperature Reporting Accuracy | -4 | 4 | % | At 100°C, with ideal NTC | 12 | ||
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | 29 | °C/W | Measured on high effective thermal conductivity test board, free air | 8 | ||
| Thermal Resistance Junction-to-Case (θJC) | θJC | 3 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
IR35201MTRPBF - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm - 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ir35201mtrpbf-etched.step/ir35201mtrpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ir35201mtrpbf.step/ir35201mtrpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (60 pp, sha256
75a639c98e1e465b, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IR35201MTRPBF
**Infineon Technologies** · DC-DC Converters · QFN-56-EP(7x7)
IR35201MTRPBF from Infineon Technologies, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ISEN6 | input | Phase 6 sensed current input (+); short to GND if not used. |
| 2 | RCSP | output | Resistor Current Sense Positive for Loop 1, connected to an external network that sets load line slope, bandwidth and temperature compensation. |
| 3 | RCSM | output | Resistor Current Sense Minus for Loop 1, connected to an external network that sets load line slope, bandwidth and temperature compensation. |
| 4 | VRDY2 | output | Open-drain Voltage Regulator Ready output for Loop 2 that asserts high when soft-start to the Loop 2 boot voltage is complete; pull up to an external voltage through a resistor. |
| 5 | VSEN | input | Loop 1 voltage sense input connected at the load, to be routed differentially with VRTN. |
| 6 | VRTN | input | Loop 1 voltage sense return input connected to Loop 1 ground at the load, to be routed differentially with VSEN. |
| 7 | NC | unconnected | Do not connect. |
| 8 | I_IN | input | Input current signal ranging from 0 to 1.25Vdc, indicating a maximum input current of 62.5 A. |
| 9 | TSEN1 | input | Loop 1 temperature sense input for an NTC network or IR PowIRstage temperature output, used for VRHOT and OTP; PowIRstage output must be scaled to 4.88mV/°C with a 0.365Vdc offset. |
| 10 | CFILT | output | 1.8V decoupling pin for the internal 1.8V supply, requiring a 1µF capacitor. |
| 11 | VRDY1 | output | Open-drain Voltage Regulator Ready output for Loop 1 that asserts high when soft-start to the Loop 1 boot voltage is complete; pull up to an external voltage through a resistor. |
| 12 | EN_L2/PWROK/CAT_FLT | input | Multiplexed pin: Enable input for Loop 2, PWROK power-OK input (AMD) that returns to Boot voltage when low and uses the SVI bus when high, or CAT_FLT CMOS output driven to VCC on output OVP, NVM CRC error or TSEN fault. |
| 13 | NC | unconnected | Do not connect. |
| 14 | VINSEN | input | Input supply voltage sense used to detect and measure a valid VR input supply, typically 4.5V-13.2V. |
| 15 | NC | unconnected | Do not connect. |
| 16 | SV_ADDR/VDDIO | input | Multiplexed pin: SV_ADDR serial VID address input where a resistor to ground sets the NVM SVID address offset and requires 0.01µF to ground, or VDDIO (AMD) supply to which the SVT line and SVD Acknowledge are driven high. |
| 17 | SV_ALERT#/SVT | output | Multiplexed pin: SV_ALERT# open output pulled low to alert the CPU of IMVP8/VR12/VR12.5 status changes (Intel), or SVT telemetry and VOTF information output (AMD); pull up through a resistor. |
| 18 | SV_CLK | input | Serial VID clock input driven by the CPU master. |
| 19 | SV_DIO | bidirectional | Serial VID bi-directional data line over which the CPU master issues commands and receives data from the controller. |
| 20 | VRHOT_ICRIT# | output | Active-low alert output that asserts when temperature or average load current exceeds user-definable thresholds; pull up to an external voltage through a resistor. |
| 21 | EN | input | VR enable input that powers the regulator when Vin and Vcc are present; it is not pulled up internally, polarity is bit-settable, and it cannot be left floating. |
| 22 | ADDR_PROT | bidirectional | Address resistor offset and I2C bus protection pin; a resistor to ground sets the NVM I2C address offset, then it acts as a logic input to enable or disable I2C communication, requiring 0.01µF to ground for noise filtering. |
| 23 | SM_ALERT# | output | Active-low SMBus/PMBus alert output indicating regulator status change; requires a pull-up, or ground if not used. |
| 24 | SM_DIO | bidirectional | I2C/SMBus/PMBus bi-directional serial data line; ground if not used. |
| 25 | SM_CLK | input | I2C/SMBus/PMBus clock input rated to 1 MHz; ground if not used. |
| 26 | PIN_ALERT# | output | Active-low alert output that asserts when input power exceeds a user-defined threshold; pull up to an external voltage through a resistor. |
| 27 | TSEN2/VAUXSEN | output | Multiplexed pin: Loop 2 temperature sense input for an NTC network or IR PowIRstage temperature output for VRHOT (float if not used), or auxiliary voltage sense input monitoring an additional supply for Vcc and driver operation (float if not used). |
| 28 | PWM1 | output | Phase 1 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 29 | PWM2 | output | Phase 2 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 30 | PWM3 | output | Phase 3 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 31 | PWM4 | output | Phase 4 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 32 | PWM5 | output | Phase 5 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 33 | PWM6 | output | Phase 6 PWM output to the input of an external MOSFET gate driver, high-impedance until ENABLE goes active; float if not used. |
| 34 | PWM7/PWM2_L2 | output | Multiplexed pin: Phase 7 PWM output, or Loop 2 Phase 2 PWM output, each connected to an external MOSFET gate driver input, high-impedance until ENABLE goes active; float if not used. |
| 35 | PWM8/PWM1_L2 | output | Multiplexed pin: Phase 8 PWM output, or Loop 2 Phase 1 PWM output, each connected to an external MOSFET gate driver input, high-impedance until ENABLE goes active; float if not used. |
| 36 | VRTN_L2 | input | Loop 2 voltage sense return input connected to Loop 2 ground at the load, to be routed differentially with VSEN_L2; short to GND if not used. |
| 37 | VSEN_L2 | input | Loop 2 voltage sense input connected to the Loop 2 VR output at the load, to be routed differentially with VRTN_L2; short to GND if not used. |
| 38 | VCC | power_in | 3.3V input supply voltage to power the device (absolute maximum 4.0V). |
| 39 | RCSM_L2 | input | Loop 2 resistor current sense minus connected to an external load-line/bandwidth/temperature network; connect to RCSP_L2 with 10kΩ if not used. |
| 40 | RCSP_L2 | input | Loop 2 resistor current sense positive connected to an external network that sets load-line slope, bandwidth and temperature compensation. |
| 41 | NC | unconnected | Do not connect. |
| 42 | ISEN1_L2/ISEN8 | input | Multiplexed pin: Loop 2 Phase 1 sensed current input (+), or Phase 8 sensed current input (+); short to GND if not used. |
| 43 | IRTN1_L2/IRTN8 | input | Multiplexed pin: Loop 2 Phase 1 sensed current return input (-), or Phase 8 sensed current return input (-); short to GND if not used. |
| 44 | ISEN2_L2/ISEN7 | input | Multiplexed pin: Loop 2 Phase 2 sensed current input (+), or Phase 7 sensed current input (+); short to GND if not used. |
| 45 | IRTN2_L2/IRTN7 | input | Multiplexed pin: Loop 2 Phase 2 sensed current return input (-), or Phase 7 sensed current return input (-); short to GND if not used. |
| 46 | ISEN5 | input | Phase 5 sensed current input (+); short to GND if not used. |
| 47 | IRTN5 | input | Phase 5 sensed current return input (-); short to GND if not used. |
| 48 | ISEN4 | input | Phase 4 sensed current input (+); short to GND if not used. |
| 49 | IRTN4 | input | Phase 4 sensed current return input (-); short to GND if not used. |
| 50 | ISEN3 | input | Phase 3 sensed current input (+); short to GND if not used. |
| 51 | IRTN3 | input | Phase 3 sensed current return input (-); short to GND if not used. |
| 52 | ISEN2 | input | Phase 2 sensed current input (+); short to GND if not used. |
| 53 | IRTN2 | input | Phase 2 sensed current return input (-); short to GND if not used. |
| 54 | ISEN1 | input | Phase 1 sensed current input (+); short to GND if not used. |
| 55 | IRTN1 | input | Phase 1 sensed current return input (-); short to GND if not used. |
| 56 | IRTN6 | input | Phase 6 sensed current return input (-); short to GND if not used. |
| 57 | GND | power_in | Ground reference for the IC; the large metal pad on the bottom must be connected to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | QFN-56-EP(7x7) |
| Category | Power Management ICs |
| Pins | 57 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC) | VCC | -0.3 | | 4 | V | Referenced to GND; min printed as GND-0.3V | 8 |
| RCSPx, RCSMx voltage | | 0 | | 2.2 | V | | 8 |
| VSEN, VRTN, ISENx, IRTNx voltage | | -0.2 | | | V | Max printed as VCC + 0.3V | 8 |
| CFILT, VINSEN, I_IN voltage | | -0.2 | | 2.2 | V | | 8 |
| TSENx voltage | | -0.3 | | | V | Max printed as VCC | 8 |
| SV_CLK, SV_DIO, SV_ALERT#, SV_ADDR voltage | | -0.3 | | | V | Max printed as VCC | 8 |
| VRDYx, ENx, ADDR_PROT, VRHOT_ICRIT#, PIN_ALERT# voltage | | -0.3 | | | V | Max printed as VCC | 8 |
| PWMx voltage | | -0.3 | | 4.1 | V | | 8 |
| SM_DIO, SM_CLK, SM_ALERT# voltage | | -0.3 | | 5.5 | V | | 8 |
| Maximum Operating Junction Temperature | | -40 | | 125 | °C | | 8 |
| Maximum Storage Temperature Range | | -65 | | 150 | °C | | 8 |
| Recommended Operating Ambient Temperature Range | | -40 | | 85 | °C | | 9 |
| Supply Voltage Range | | 2.9 | | 3.63 | V | | 9 |
| Supply Voltage | Vcc | 2.9 | 3.3 | 3.63 | V | | 9 |
| 3.3V UVLO Turn-on Threshold | | | 2.8 | 2.9 | V | | 9 |
| 3.3V UVLO Turn-off Threshold | | 2.6 | 2.7 | | V | | 9 |
| Input Impedance (VINSEN) | | 1 | | | MΩ | | 9 |
| Input Range V12 | | 0 | 0.857 | 1.1 | V | With 14:1 divider | 9 |
| UVLO Turn-on Programmable Range | | 4.5 | | 13.2 | V | With 14:1 divider | 9 |
| UVLO Turn-off Programmable Range | | 4.5 | | 13.2 | V | With 14:1 divider | 9 |
| OVP Threshold (if enabled) | | 14.3 | 14.6 | 14.9 | V | If enabled | 9 |
| AUX Voltage UVLO Turn-on Threshold | VAUXSEN_on | 0.642 | 0.664 | 0.686 | mV | | 9 |
| AUX Voltage UVLO Turn-off Threshold | VAUXSEN_off | 0.564 | 0.586 | 0.608 | mV | | 9 |
| System Accuracy | | -1.1 | | 1.1 | %VID | VID = 2.005-3.04V; 0 to 85°C ambient | 9 |
| System Accuracy | | -0.5 | | 0.5 | %VID | VID = 1.0V-2.0V; 0 to 85°C ambient | 9 |
| System Accuracy | | -5 | | 5 | mV | VID = 0.8-0.995V; 0 to 85°C ambient | 9 |
| System Accuracy | | -8 | | 8 | mV | VID = 0.25-0.795V; 0 to 85°C ambient | 9 |
| System Accuracy | | -1.65 | | 1.65 | %VID | VID = 2.005-3.04V; -40°C to 125°C junction | 9 |
| System Accuracy | | -0.75 | | 0.75 | %VID | VID = 1.0V-2.0V; -40°C to 125°C junction | 9 |
| System Accuracy | | -7.5 | | 7.5 | mV | VID = 0.8-0.995V; -40°C to 125°C junction | 9 |
| System Accuracy | | -12 | | 12 | mV | VID = 0.25-0.795V; -40°C to 125°C junction | 9 |
| Frequency Accuracy | | -2.5 | | 2.5 | % | 0°C to 85°C | 9 |
| Frequency Accuracy | | -5 | | 5 | % | -40°C to 125°C | 9 |
| PWM Frequency Range | | 194 | | 2000 | kHz | | 9 |
| NTC Output Current | TSEN_NTC | 96 | 100 | 104 | µA | For TSEN = 0 to 1.2V | 10 |
| NTC Temperature Sense Accuracy | | 96 | | 104 | °C | At 100°C (ideal NTC) | 10 |
| Digital Input High Voltage (Type 1) | | 0.7 | | | V | EN(_L2), VRHOT_ICRIT# (during PoR) | 10 |
| Digital Input Low Voltage (Type 1) | | | | 0.35 | V | EN(_L2), VRHOT_ICRIT# (during PoR) | 10 |
| Digital Input Leakage Current (Type 1) | | -5 | | 5 | µA | Vpad = 0 to 2V | 10 |
| Digital Input High Voltage (Type 2) | | 0.65 | | | V | SV_CLK, SV_DIO | 10 |
| Digital Input Low Voltage (Type 2) | | | | 0.45 | V | SV_CLK, SV_DIO | 10 |
| Digital Input Leakage Current (Type 2) | | -1 | | 1 | µA | Vpad = 0 to 2V | 10 |
| LVTTL Input High Voltage | | 2.1 | | | V | SM_DIO, SM_CLK, EN(_L2), ADDR_PROT | 10 |
| LVTTL Input Low Voltage | | | | 0.8 | V | SM_DIO, SM_CLK, EN(_L2), ADDR_PROT | 10 |
| LVTTL Input Leakage | | -1 | | 1 | µA | Vpad = 0 to 3.6V | 10 |
| VSEN Input Current | | -25 | | 100 | µA | VCPU = 0.5V to 3.04V | 10 |
| Differential Input Voltage Range | | 0 | | 3.04 | V | VRTN = ±100mV | 10 |
| Remote Current Sense Input Voltage Range (ISENx/IRTNx) | | -0.1 | | | V | Max printed as VCC - 0.65 | 10 |
| Analog Address/Level Inputs Output Current | | 96 | 100 | 104 | µA | Vpad = 0 to 1.2V | 10 |
| CAT_FLT Output Low Voltage | | | | 0.4 | V | Iol = 20mA | 10 |
| Open-Drain Output Low Voltage | | | | 0.3 | V | 4mA drive | 10 |
| OVP Operating Threshold (programmable) | | 50 | | 400 | mV | Relative to VID | 12 |
| Output UVP Threshold (programmable) | | 50 | | 400 | mV | Relative to VID | 12 |
| Fast OCP Range (per phase) | | 0 | | 62 | A | | 12 |
| OCP System Accuracy | | -2 | | 2 | % | System excluding DCR/sense resistor | 12 |
| VR_HOT Range | | 64 | | 127 | °C | | 12 |
| OTP Range (added to VR_HOT level) | | 0 | | 31 | °C | | 12 |
| Temperature Reporting Accuracy | | -4 | | 4 | % | At 100°C, with ideal NTC | 12 |
| Thermal Resistance Junction-to-Ambient (θJA) | θJA | | 29 | | °C/W | Measured on high effective thermal conductivity test board, free air | 8 |
| Thermal Resistance Junction-to-Case (θJC) | θJC | | 3 | | °C/W | | 8 |
## CAD (KiCad official)
- Symbol: `IR35201MTRPBF`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm`
- 3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `ir35201mtrpbf-etched.step` / `ir35201mtrpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ir35201mtrpbf.step` / `ir35201mtrpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](docs/ir35201mtrpbf-datasheet.pdf) (60 pp, sha256 `75a639c98e1e465b`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ir35201mtrpbf-datasheet.pdf)