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IR2183STRPBF

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Infineon Technologies Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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IR2183STRPBF

Infineon Technologies · Gate Drivers · SOIC-8

IR2183STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HIN input Logic input for the high side gate driver output (HO), in phase and referenced to COM; VIH minimum is 2.7 V, VIL maximum is 0.8 V, and the pin is internally clamped with a 5.2 V zener diode.
2 LIN input Logic input for the low side gate driver output (LO), out of phase and referenced to COM; VIH minimum is 2.7 V, VIL maximum is 0.8 V, and the pin is internally clamped with a 5.2 V zener diode.
3 COM power_in Low side return; all voltage parameters in the absolute maximum ratings are referenced to COM.
4 LO output Low side gate driver output, switching between 0 V and VCC, with pulsed source current of at least 1.4 A and sink current of at least 1.8 A (PW ≤ 10 µs).
5 VCC power_in Low side and logic fixed supply, recommended operating range 10 V to 20 V (absolute maximum -0.3 V to 25 V).
6 VS power_in High side floating supply return, with offset voltage recommended up to 600 V and allowable dVS/dt transient of 50 V/ns.
7 HO output High side floating gate driver output, operating between VS and VB (VHO absolute range VS - 0.3 V to VB + 0.3 V).
8 VB power_in High side floating supply, recommended operating range VS + 10 V to VS + 20 V (absolute maximum 625 V).

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High side floating absolute voltage VB -0.3 625 V 2
Low side and logic fixed supply voltage VCC -0.3 25 V 2
Low side output voltage VLO -0.3 V 2
Allowable offset supply voltage transient dVS/dt 50 V/ns 2
Package power dissipation (8-lead SOIC) PD 0.625 W TA ≤ +25°C 2
Thermal resistance, junction to ambient (8-lead SOIC) RthJA 200 °C/W 8-lead SOIC 2
Junction temperature TJ 150 °C 2
Storage temperature TS -50 150 °C 2
Lead temperature (soldering) TL 300 °C soldering, 10 seconds 2
High side floating supply offset voltage VS 600 V Note 1 2
Low side and logic fixed supply voltage VCC 10 20 V 2
Low side output voltage VLO 0 V 2
Ambient temperature TA -40 125 °C 2
Logic "1" input voltage for HIN & logic "0" for LIN VIH 2.7 V VCC = 10V to 20V 3
Logic "0" input voltage for HIN & logic "1" for LIN VIL 0.8 V VCC = 10V to 20V 3
High level output voltage, VBIAS - VO VOH 1.2 V IO = 0A 3
Low level output voltage, VO VOL 0.1 V IO = 0A 3
Offset supply leakage current ILK 50 µA VB = VS = 600V 3
Quiescent VBS supply current IQBS 20 60 150 µA VIN = 0V or 5V 3
Quiescent VCC supply current IQCC 0.4 1 1.6 mA VIN = 0V or 5V 3
Logic "1" input bias current IIN+ 25 60 µA HIN = 5V, LIN = 0V 3
Logic "0" input bias current IIN- 1 µA HIN = 0V, LIN = 5V 3
VCC and VBS supply undervoltage positive going threshold (VCCUV+) VCCUV+ 8 8.9 9.8 V 3
VCC and VBS supply undervoltage positive going threshold (VBSUV+) VBSUV+ 8 8.9 9.8 V 3
VCC and VBS supply undervoltage negative going threshold (VCCUV-) VCCUV- 7.4 8.2 9 V 3
VCC and VBS supply undervoltage negative going threshold (VBSUV-) VBSUV- 7.4 8.2 9 V 3
VCC undervoltage hysteresis VCCUVH 0.3 0.7 V 3
VBS undervoltage hysteresis VBSUVH 0.3 0.7 V 3
Output high short circuit pulsed current IO+ 1.4 1.9 A VO = 0V, PW ≤ 10 µs 3
Output low short circuit pulsed current IO- 1.8 2.3 A VO = 15V, PW ≤ 10 µs 3
Turn-on propagation delay ton 180 270 ns VS = 0V 3
Turn-off propagation delay toff 220 330 ns VS = 0V or 600V 3
Delay matching /ton - toff/ MT 0 35 ns 3
Turn-on rise time tr 40 60 ns VS = 0V 3
Turn-off fall time tf 20 35 ns VS = 0V 3
Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) DT 280 400 520 ns RDT = 0 3
Deadtime matching /DTLO-HO - DTHO-LO/ MDT 0 50 ns RDT = 0 3

CAD (KiCad official)

  • Symbol: IR2183STRPBF
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ir2183strpbf-etched.step / ir2183strpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ir2183strpbf.step / ir2183strpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (22 pp, sha256 a4ff215a37fe3822, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF