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IR21364STRPBF

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Infineon Technologies Gate Drive ICs, SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsir21364strpbffactory-2.0.0extractor-text

Verified IR21364STRPBF

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: IR21364STRPBF · SOIC-28-300mil · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C537592, digikey IR21364STRPBFTR-ND, mouser 942-IR21364STRPBF
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ag1k_6ie/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ir21364strpbf.kicad_sym✓ ir21364strpbf.kicad_mod✓ ir21364strpbf.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers ir21364strpbf: viewers · Ray 8d ago
ir21364strpbf-etched.glb Publish 0.1.0 · Ray 8d ago
ir21364strpbf-etched.step ir21364strpbf: factory component page (tier=mfr) · Ray 8d ago
ir21364strpbf-hero.glb ir21364strpbf: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
ir21364strpbf-hero.overlay.json Publish 0.1.0 · Ray 8d ago
ir21364strpbf.glb Publish 0.1.0 · Ray 8d ago
ir21364strpbf.kicad_mod Publish 0.1.0 · Ray 8d ago
ir21364strpbf.kicad_sym Publish 0.1.0 · Ray 8d ago
ir21364strpbf.lbr Publish 0.1.0 · Ray 8d ago
ir21364strpbf.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
verification.json Verified: Published by the parts factory: tier mfr, 28 pins · Ray 8d ago

IR21364STRPBF

Infineon Technologies · Gate Drive ICs · SOIC-28-300mil

IR21364STRPBF from Infineon Technologies, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low side supply voltage, recommended 11.5 V to 20 V (absolute max 25 V).
2 HIN1 input Logic input for high side gate driver output HO1, in phase; 3.3 V logic compatible.
3 HIN2 input Logic input for high side gate driver output HO2, in phase; 3.3 V logic compatible.
4 HIN3 input Logic input for high side gate driver output HO3, in phase; 3.3 V logic compatible.
5 LIN1 input Logic input for low side gate driver output LO1, in phase; 3.3 V logic compatible.
6 LIN2 input Logic input for low side gate driver output LO2, in phase; 3.3 V logic compatible.
7 LIN3 input Logic input for low side gate driver output LO3, in phase; 3.3 V logic compatible.
8 FAULT output Active-low open-drain output indicating an over-current (ITRIP) or low-side undervoltage lockout has occurred.
9 ITRIP input Analog input for overcurrent shutdown that turns off all outputs and activates FAULT and RCIN low; threshold typically 0.46 V.
10 EN input Positive-logic enable input; I/O logic functions when EN is high, with no effect on FAULT and not latched.
11 RCIN input External RC network input that sets the FAULT clear delay tFLTCLR of about R*C; FAULT releases when RCIN exceeds 8 V.
12 VSS power_in Logic ground.
13 COM power_in Low side gate drivers return.
14 LO3 output Low side gate driver output for phase 3.
15 LO2 output Low side gate driver output for phase 2.
16 LO1 output Low side gate driver output for phase 1.
17 NC unconnected No pin is drawn at this position in the package drawing (removed lead).
18 VS3 passive High voltage floating supply return for phase 3, up to 600 V offset.
19 HO3 output High side gate driver output for phase 3.
20 VB3 power_in High side floating supply for phase 3, VS3 +11.5 V to VS3 +20 V.
21 NC unconnected No pin is drawn at this position in the package drawing (removed lead).
22 VS2 passive High voltage floating supply return for phase 2, up to 600 V offset.
23 HO2 output High side gate driver output for phase 2.
24 VB2 power_in High side floating supply for phase 2, VS2 +11.5 V to VS2 +20 V.
25 NC unconnected No pin is drawn at this position in the package drawing (removed lead).
26 VS1 passive High voltage floating supply return for phase 1, up to 600 V offset.
27 HO1 output High side gate driver output for phase 1.
28 VB1 power_in High side floating supply for phase 1, VS1 +11.5 V to VS1 +20 V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-28-300mil
Category Power Management ICs
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High side floating supply voltage VB -0.3 625 V 3
Low side and logic fixed supply voltage VCC -0.3 25 V 3
Allowable offset voltage slew rate dV/dt 50 V/ns 3
Package power dissipation (28 lead SOIC) PD 1.6 W TA ≤ +25 °C 3
Thermal resistance, junction to ambient (28 lead SOIC) RthJA 78 °C/W 3
Junction temperature TJ 150 °C 3
Storage temperature TS -55 150 °C 3
Lead temperature (soldering, 10 seconds) TL 300 °C 3
High side floating supply voltage (VS1,2,3) VS 600 V Note 1 3
Low side supply voltage VCC 11.5 20 V IR21364 3
Low side output voltage VLO1,2,3 0 V max printed as VCC 3
Logic ground VSS -5 5 V 3
Ambient temperature TA -40 125 °C 3
Logic "0" input voltage VIH 0.8 V 4
Logic "1" input voltage VIL 2.5 V 4
Enable positive going threshold VEN,TH+ 2.5 V 4
Enable negative going threshold VEN,TH- 0.8 V 4
ITRIP positive going threshold VIT,TH+ 0.37 0.46 0.55 V 4
High level output voltage, VBIAS - VO VOH 0.9 1.4 V Io = 20 mA 4
Low level output voltage, VO VOL 0.4 0.6 V Io = 20 mA 4
VCC supply undervoltage positive going threshold VCCUV+ 9.6 10.4 11.2 V IR21364 4
VCC supply undervoltage negative going threshold VCCUV- 8.6 9.4 10.2 V IR21364 4
VBS supply undervoltage positive going threshold VBSUV+ 9.6 10.4 11.2 V IR21364 4
VBS supply undervoltage negative going threshold VBSUV- 8.6 9.4 10.2 V IR21364 4
Offset supply leakage current llk 50 µA VB = VS = 600 V 4
Quiescent VBS supply current IQBS 70 120 µA VB1,2,3 = VS1,2,3 = 600 V 4
Quiescent VCC supply current IQCC 0.6 1.3 mA VIN = 0 V or 5 V 4
Input bias current (LOUT = HI) ILIN+ 100 195 µA VLIN = 3.3 V 4
Input bias current (LOUT = LO) ILIN- -1 µA VLIN = 0 V 4
Input bias current (HOUT = HI) IHIN+ 100 195 µA VHIN = 3.3 V 4
Input bias current (HOUT = LO) IHIN- -1 µA VHIN = 0 V 4
"High" ITRIP input bias current IITRIP+ 3.3 6 µA VITRIP = 3.3 V 4
"Low" ITRIP input bias current IITRIP- -1 µA VITRIP = 0 V 4
"Low" ENABLE input bias current IEN- -1 µA VEN = 0 V 4
RCIN input bias current IRCIN 1 µA Vrcin = 0 V or 15 V 4
Output high short circuit pulsed current Io+ 120 200 mA Vo = 0 V, PW ≤ 10 µs 4
Output low short circuit pulsed current Io- 250 350 mA Vo = 15 V, PW ≤ 10 µs 4
RCIN low on resistance Ron_RCIN 50 100 Ω I = 1.5 mA 4
FAULT low on resistance Ron_FAULT 50 100 Ω I = 1.5 mA 4
Turn-on propagation delay ton 350 500 650 ns VIN = 0 V & 5 V 5
Turn-off propagation delay toff 375 530 685 ns VIN = 0 V & 5 V 5
Turn-on rise time tr 125 190 ns 5
Turn-off fall time tf 50 75 ns 5
ENABLE low to output shutdown propagation delay tEN 300 450 600 ns VIN, VEN = 0 V or 5 V 5
ITRIP to output shutdown propagation delay tITRIP 500 750 1000 ns VITRIP = 5 V 5
ITRIP blanking time tbl 100 150 ns VIN = 0 V or 5 V 5
ITRIP to FAULT propagation delay tFLT 400 600 800 ns VITRIP = 5 V 5
Input filter time (HIN, LIN) tFILIN 100 200 ns VIN = 0 V & 5 V 5
Enable input filter time tfilterEn 100 200 ns VIN = 0 V & 5 V 5
Deadtime DT 220 290 360 ns VIN = 0 V & 5 V 5
Ton, off matching time (on all six channels) MT 75 ns External dead time >450 nsec 5
DT matching (Hi->Lo & Lo->Hi on all channels) MDT 70 ns External dead time >450 nsec 5
Pulse width distortion (pwin-pwout) PM 75 ns PW input =10 µs 5
FAULT clear time tFLTCLR 1.3 1.65 2 ms RCIN: R = 2 MΩ, C = 1 nF; VIN = 0 V or 5 V; VITRIP = 0 V 5

CAD (KiCad official)

  • Symbol: IR21364STRPBF
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: ir21364strpbf-etched.step / ir21364strpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ir21364strpbf.step / ir21364strpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (20 pp, sha256 c145cc055de4d3e4, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF