# IR21271STR

**UMW** · Gate Drivers · SOP-8

IR21271STR from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side and main power supply; recommended range is 8 V to 20 V, with an absolute maximum of -0.3 V to 22 V. |
| 2 | IN | input | Logic input for the high-side gate driver output (HO), in phase with HO; VIH minimum is 2.5 V, VIL maximum is 0.8 V, and the recommended range is 0 V to VCC. |
| 3 | FAULT | output | Open-drain, negative-logic indicator that goes low when an over-current shutdown has occurred; output voltage is rated -0.3 V to VCC + 0.3 V. |
| 4 | VSS | power_in | Logic ground; all voltage parameters are referenced to VSS. |
| 5 | VS | power_in | High-side floating supply return; recommended range is -5 V to 300 V, with transient negative VS of -50 V allowed for a 50 ns pulse. |
| 6 | CS | input | Current sense input to the current sense comparator; the positive-going threshold is 1.8 V typical (1.5 V to 2.1 V), and the recommended signal range is VS to VS + 5 V. |
| 7 | HO | output | High-side gate drive output, swinging between VS and VB to drive the high-side N-channel MOSFET or IGBT. |
| 8 | VB | power_in | High-side floating bootstrap supply; recommended range is VS + 8 V to VS + 20 V, with an absolute maximum of -0.3 V to 322 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High side floating supply voltage (VB) | VB | -0.3 |  | 322 | V |  | 3 |
| Low side and main power supply (VCC) | VCC | -0.3 |  | 22 | V |  | 3 |
| dVS/dt allowable offset supply voltage transient | dVS/dt |  |  | 50 | V/ns |  | 3 |
| Package power dissipation | PD |  |  | 0.625 | W | TA ≤25°C | 3 |
| Junction to ambient thermal resistance | RthJA |  |  | 200 | °C/W |  | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 3 |
| Lead temperature (soldering) | TL |  |  | 300 | °C | Soldering, 10 seconds | 3 |
| High side floating supply return (VS) | VS | -5 |  | 300 | V |  | 4 |
| Low side and main power supply (VCC) | VCC | 8 |  | 20 | V |  | 4 |
| Logic input of IN | VIN | 0 |  |  | V |  | 4 |
| FAULT output voltage | VFLT | 0 |  |  | V |  | 4 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 4 |
| Turn-on propagation delay | tON |  | 150 | 250 | ns | VS=0V | 4 |
| Turn-off propagation delay | tOFF |  | 150 | 250 | ns | VS=300V | 4 |
| Turn-on rise time | tR |  | 80 | 130 | ns |  | 4 |
| Turn-off fall time | tF |  | 40 | 70 | ns |  | 4 |
| Start-up blanking time | tBL | 550 | 750 | 950 | ns |  | 4 |
| CS shutdown propagation delay | tCS |  | 65 | 360 | ns |  | 4 |
| CS to FAULT pull-up propagation delay | tflt |  | 270 | 510 | ns |  | 4 |
| Logic 1 (IN) input voltage | VIH | 2.5 |  |  | V |  | 5 |
| Logic 0 (IN) input voltage | VIL |  |  | 0.8 | V | VCC=10Vto 20V | 5 |
| CS input positive going threshold | VCSTH+ | 1.5 | 1.8 | 2.1 | V |  | 5 |
| VBS supply UVLO threshold (positive going) | VBSUV+ | 6.3 | 7.2 | 8.2 | V |  | 5 |
| VBS supply UVLO threshold (negative going) | VBSUV- | 6 | 6.8 | 7.7 | V |  | 5 |
| High-side floating supply leakage current | ILK |  |  | 50 | μA | VB=VS=300V | 5 |
| Quiescent VB supply current | IQBS |  | 300 | 800 | μA | VIN=0V or 5V | 5 |
| Quiescent VCC supply current | IQCC |  | 60 | 120 | μA | VIN=0V or 5V | 5 |
| High CS bias current (CS=3V) | ICS+ |  |  | 5 | μA | CS=3V | 5 |
| High CS bias current (CS=0V) | ICS- |  |  | 5 | μA | CS=0V | 5 |
| High level output voltage, VBIAS - VO | VOH |  |  | 0.2 | V | IO=2mA | 5 |
| Low level output voltage, VO | VOL |  |  | 0.1 | V |  | 5 |
| Logic 1 input bias current | IIN+ |  | 7 | 15 | μA | VIN=5V | 5 |
| Logic 0 input bias current | IIN- |  | 0 | 5 | μA | VIN=0V | 5 |
| Output high short circuit pulsed current | IO+ | 200 | 300 |  | mA | VO=0V PW≤10us | 5 |
| Output low short circuit pulsed current | IO- | 420 | 600 |  | mA | VO=15V PW≤10us | 5 |

## CAD (KiCad official)

- Symbol: `IR21271STR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ir21271str-etched.step` / `ir21271str-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ir21271str.step` / `ir21271str.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590921133267243008) (11 pp, sha256 `d9c612fc7528d911`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ir21271str-datasheet.pdf)