component
IR2110S-MNS
Public Made by Adomby adom
Minos Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIR2110S-MNS
Minos · Gate Drivers · SOIC-16-300mil
IR2110S-MNS from Minos, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LO | output | Low-side gate driver output, which drives the low-side N-channel MOSFET/IGBT gate and is referenced to COM. |
| 2 | COM | power_in | Low-side return, the reference ground for the LO output and the VCC low-side supply. |
| 3 | VCC | power_in | Low-side supply voltage for the LO gate driver, recommended 10 V to 20 V with respect to COM. |
| 4 | NC | unconnected | Not connected. |
| 5 | NC | unconnected | Not connected. |
| 6 | VS | power_in | High-side floating supply return, the reference point for the HO output and the bootstrap supply, recommended range -9 V to 700 V. |
| 7 | VB | power_in | High-side floating supply for the HO gate driver, recommended VS + 10 V to VS + 20 V (bootstrap operation). |
| 8 | HO | output | High-side gate driver output, which drives the high-side N-channel MOSFET/IGBT gate and is referenced to VS. |
| 9 | NC | unconnected | Not connected. |
| 10 | NC | unconnected | Not connected. |
| 11 | VDD | power_in | Logic supply voltage for the input logic stage, recommended VSS + 3 V to VSS + 20 V. |
| 12 | HIN | input | Logic input for the high-side gate driver output HO, referenced to VSS and compatible with 3.3 V, 5 V and 15 V logic. |
| 13 | SD | input | Shutdown logic input that turns off both the HO and LO outputs when asserted. |
| 14 | LIN | input | Logic input for the low-side gate driver output LO, referenced to VSS and compatible with 3.3 V, 5 V and 15 V logic. |
| 15 | VSS | power_in | Logic ground reference for the HIN, LIN and SD inputs and the VDD logic supply, with a rated bias range of -5 V to +5 V. |
| 16 | NC | unconnected | Not connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Minos |
| Package | SOIC-16-300mil |
| Category | Motor Driver ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating supply voltage (VB) | VB | -0.3 | 725 | V | 5 | ||
| High-side floating offset voltage (VS), referenced to VB | VS | -25 | 0.3 | V | min = VB − 25.0 V; max = VB + 0.3 V | 5 | |
| High-side floating output voltage (VHO), referenced to VS (min) and VB (max) | VHO | -0.3 | 0.3 | V | min = VS − 0.3 V; max = VB + 0.3 V | 5 | |
| Low-side supply voltage (VCC) | VCC | -0.3 | 25 | V | 5 | ||
| Low-side floating output voltage (VLO), referenced to VCC | VLO | -0.3 | 0.3 | V | min = −0.3 V; max = VCC + 0.3 V | 5 | |
| Logic supply voltage (VDD), referenced to VSS | VDD | -0.3 | 25 | V | max = VSS + 25.0 V | 5 | |
| Logic supply bias voltage (VSS) | VSS | -5 | 5 | V | 5 | ||
| Logic input voltage (HIN, LIN, SD), referenced to VSS (min) and VCC (max) | VIN | -0.3 | 0.3 | V | min = VSS − 0.3 V; max = VCC + 0.3 V | 5 | |
| Allowable offset voltage slew rate | dVS/dt | 50 | V/ns | 5 | |||
| Power dissipation, 16-SOP package | PD | 1.3 | W | 16-SOP; PCB 76.2 x 114.3 x 1.6 mm (note 1,2,3) | 5 | ||
| Maximum junction temperature | TJ | 150 | ℃ | 5 | |||
| Storage temperature | TSTG | -55 | 150 | ℃ | 5 | ||
| Thermal resistance, junction to ambient, 16-SOP | θJA | 95 | ℃/W | 16-SOP; JESD51-2/3 natural convection | 5 | ||
| High-side floating supply voltage (VB), recommended | VB | 10 | 20 | V | Referenced to VS: printed VS + 10 (min) and VS + 20 (max) | 5 | |
| High-side floating supply offset voltage (VS), recommended | VS | -9 | 700 | V | 5 | ||
| High-side output voltage (VHO), recommended | VHO | 0 | 0 | V | min = VS; max = VB (offset 0 from reference) | 5 | |
| Low-side supply voltage (VCC), recommended | VCC | 10 | 20 | V | 5 | ||
| Low-side output voltage (VLO), recommended | VLO | 0 | 0 | V | min = 0 V; max = VCC (offset 0 from reference) | 5 | |
| Logic supply voltage (VDD), recommended, referenced to VSS | VDD | 3 | 20 | V | Referenced to VSS: printed VSS + 3 (min) and VSS + 20 (max) | 5 | |
| Logic supply bias voltage (VSS), recommended | VSS | -5 | 5 | V | 5 | ||
| Logic input voltage (VIN), recommended | VIN | 0 | 0 | V | min = VSS; max = VDD (offset 0 from reference) | 5 | |
| Ambient temperature (TA), recommended | TA | -40 | 125 | C | 5 | ||
| Quiescent VCC supply current | IQCC | 40 | 80 | μA | VIN = 0 V or VDD | 6 | |
| Quiescent VDD supply current | IQDD | 10 | μA | VIN = 0 V or VDD | 6 | ||
| VCC undervoltage positive-going threshold | VCCUV+ | 8 | 8.9 | 9.8 | V | VIN = 0 V, VCC = sweep | 6 |
| VCC undervoltage negative-going threshold | VCCUV− | 7.4 | 8.2 | 9 | V | VIN = 0 V, VCC = sweep | 6 |
| Quiescent VBS supply current | IQBS | 60 | 130 | μA | VIN = 0 V or VDD | 6 | |
| VBS undervoltage positive-going threshold | VBSUV+ | 8 | 8.9 | 9.8 | V | VIN = 0 V, VBS = sweep | 6 |
| VBS undervoltage negative-going threshold | VBSUV− | 7.4 | 8.2 | 9 | V | VIN = 0 V, VBS = sweep | 6 |
| Offset supply leakage current | ILK | 50 | μA | VB = VS = 700 V | 6 | ||
| Logic '1' input threshold voltage | VIH | 2.4 | V | VDD = 3 V | 6 | ||
| Logic '1' input threshold voltage | VIH | 9.5 | V | VDD = 15 V | 6 | ||
| Logic '0' input threshold voltage | VIL | 0.8 | V | VDD = 3 V | 6 | ||
| Logic '0' input threshold voltage | VIL | 6 | V | VDD = 15 V | 6 | ||
| Logic high input bias current | IIN+ | 20 | 40 | μA | VIN = VDD | 6 | |
| Logic low input bias current | IIN− | 3 | μA | VIN = 0 V | 6 | ||
| Logic input pull-down resistance | RIN | 375 | 750 | KΩ | 6 | ||
| High-level output voltage (VBIAS − VO) | VOH | 1.5 | V | No load, IO = 0 A | 6 | ||
| Low-level output voltage | VOL | 200 | mV | No load, IO = 0 A | 6 | ||
| Output high short-circuit pulsed current | IO+ | 3 | 4 | A | Vo=0 V, PW≤10μs | 6 | |
| Output low short-circuit pulsed current | IO− | 3 | 4 | A | Vo=15 V, PW≤10 μs | 6 | |
| VSS-COM / COM-VSS voltage withstand | VSS/COM | -5 | 5 | V | 6 | ||
| Allowable negative VS voltage while HIN propagates to HO | -VS | -9.8 | -7 | V | 6 | ||
| Turn-on propagation delay | ton | 130 | 200 | ns | VS = 0 V | 7 | |
| Turn-off propagation delay | toff | 130 | 200 | ns | VS=700V | 7 | |
| Shutdown propagation delay (note 5) | tsd | 130 | 200 | ns | VS=700V | 7 | |
| Turn-on rise time | tr | 25 | 35 | ns | 7 | ||
| Turn-off fall time | tf | 17 | 25 | ns | 7 | ||
| Delay matching, HO and LO on/off | MT | 10 | ns | 7 |
CAD (KiCad official)
- Symbol:
IR2110S-MNS - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ir2110s-mns-etched.step/ir2110s-mns-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ir2110s-mns.step/ir2110s-mns.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Minos datasheet (16 pp, sha256
9eae9aac76f56461, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).