# IR2011SPBF

**Infineon Technologies** · Gate Drivers · SOIC-8

IR2011SPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low side fixed supply, recommended 10 to 20V (absolute maximum 25V), with undervoltage lockout. |
| 2 | VB | power_in | High side floating supply, VS + 10V to VS + 20V recommended (absolute maximum 225V), with undervoltage lockout. |
| 3 | HO | output | High side gate drive output, swings from VS to VB with 1.0A typical source/sink pulsed current. |
| 4 | VS | power_in | High side floating supply return, operational up to 200V offset. |
| 5 | HIN | input | Logic input for high side gate driver output HO, in phase, active high, 3.3V/5V compatible Schmitt trigger with pull-down. |
| 6 | LIN | input | Logic input for low side gate driver output LO, in phase, active high, 3.3V/5V compatible Schmitt trigger with pull-down. |
| 7 | COM | power_in | Low side return (ground reference for logic inputs and LO). |
| 8 | LO | output | Low side gate drive output, swings from COM to VCC with 1.0A typical source/sink pulsed current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High side floating supply voltage | VB | -0.3 |  | 225 | V | referenced to COM | 3 |
| Low side fixed supply voltage | VCC | -0.3 |  | 25 | V | referenced to COM | 3 |
| Allowable offset supply voltage transient | dVs/dt |  |  | 50 | V/ns |  | 3 |
| Package power dissipation, 8-Lead SOIC | PD |  |  | 0.625 | W | TA ≤ +25°C | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 3 |
| Lead temperature | TL |  |  | 300 | °C | soldering, 10 seconds | 3 |
| Thermal resistance, junction to ambient, 8-Lead SOIC | RthJA |  |  | 200 | °C/W | board mounted, still air | 3 |
| High side floating supply offset voltage | VS |  |  | 200 | V | VS and COM offset ratings tested with all supplies biased at 15V differential | 3 |
| Low side fixed supply voltage | VCC | 10 |  | 20 | V |  | 3 |
| Low side output voltage | VLO | 0 |  |  | V |  | 3 |
| Logic input voltage (HIN, LIN) | VIN |  |  | 5.5 | V |  | 3 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 3 |
| Turn-on rise time | tr |  | 35 | 50 | ns |  | 4 |
| Turn-off fall time | tf |  | 20 | 35 | ns |  | 4 |
| Turn-on delay matching | DM1 |  |  | 20 | ns |  | 4 |
| Turn-off delay matching | DM2 |  |  | 20 | ns |  | 4 |
| Logic "1" input voltage | VIH | 2.2 |  |  | V | VCC = 10V, 20V | 4 |
| Logic "0" input voltage | VIL |  |  | 0.7 | V | VCC = 10V, 20V | 4 |
| High level output voltage, VBIAS - VO | VOH |  |  | 2 | V | IO = 0A | 4 |
| Low level output voltage, VO | VOL |  |  | 0.2 | V | IO = 20mA | 4 |
| Offset supply leakage current | ILK |  |  | 50 | μA | VB = VS = 200V | 4 |
| Quiescent VBS supply current | IQBS |  | 90 | 210 | μA | VIN = 0V or 3.3V | 4 |
| Quiescent VCC supply current | IQCC |  | 140 | 230 | μA |  | 4 |
| Logic "1" input bias current | IIN+ |  | 7 | 20 | μA | VIN = 3.3V | 4 |
| Logic "0" input bias current | IIN- |  |  | 1 | μA | VIN = 0V | 4 |
| VBS supply undervoltage positive going threshold | VBSUV+ | 8.2 | 9 | 9.8 | V |  | 4 |
| VBS supply undervoltage negative going threshold | VBSUV- | 7.4 | 8.2 | 9 | V |  | 4 |
| VCC supply undervoltage positive going threshold | VCCUV+ | 8.2 | 9 | 9.8 | V |  | 4 |
| VCC supply undervoltage negative going threshold | VCCUV- | 7.4 | 8.2 | 9 | V |  | 4 |

## CAD (KiCad official)

- Symbol: `IR2011SPBF`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ir2011spbf-etched.step` / `ir2011spbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ir2011spbf.step` / `ir2011spbf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913593119084544) (18 pp, sha256 `72096d02f797d750`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ir2011spbf-datasheet.pdf)