Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	10d ago
viewers	ir1168strpbf: viewers · Ray	10d ago
ir1168strpbf-etched.glb	Publish 0.1.0 · Ray	10d ago
ir1168strpbf-etched.step	ir1168strpbf: factory component page (tier=mfr) · Ray	10d ago
ir1168strpbf-hero.glb	ir1168strpbf: hero GLB from the etched model (keeps the MPN mark) · Ray	10d ago
ir1168strpbf-hero.overlay.json	Publish 0.1.0 · Ray	10d ago
ir1168strpbf.glb	Publish 0.1.0 · Ray	10d ago
ir1168strpbf.kicad_mod	Publish 0.1.0 · Ray	10d ago
ir1168strpbf.kicad_sym	Publish 0.1.0 · Ray	10d ago
ir1168strpbf.lbr	Publish 0.1.0 · Ray	10d ago
ir1168strpbf.step	Publish 0.1.0 · Ray	10d ago
package.json	Publish 0.1.0 · Ray	10d ago
page.json	Set visibility: public · Ray	10d ago
README.md	Publish 0.1.0 · Ray	10d ago

IR1168STRPBF

Infineon Technologies · Monitors & Reset Circuits · SOP-8

IR1168STRPBF from Infineon Technologies, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GATE1	output	Gate drive output 1 for the first synchronous rectifier MOSFET, internally clamped with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended especially when MOSFETs are paralleled.
2	VCC	power_in	Supply voltage pin monitored by the UVLO circuit, with a supply operating range of 8.6 V to 18 V, and it is not internally clamped and should be bypassed close to the IC.
3	VS1	input	Differential source voltage sense for synchronous FET 1, which must not be tied directly to GND (pin 7) and must instead be a Kelvin contact as close as possible to the MOSFET source pin.
4	VD1	input	High-voltage drain voltage sense for synchronous FET 1, rated for a continuous drain sense voltage of -3 V to 200 V and requiring optimized routing between the MOSFET drain and this pin.
5	VD2	input	High-voltage drain voltage sense for synchronous FET 2, rated for a continuous drain sense voltage of -3 V to 200 V and requiring optimized routing between the MOSFET drain and this pin.
6	VS2	input	Differential source voltage sense for synchronous FET 2, which must not be tied directly to GND (pin 7) and must instead be a Kelvin contact as close as possible to the MOSFET source pin.
7	GND	power_in	Analog and power ground; the internal control circuit and gate drivers are referenced to this pin.
8	GATE2	output	Gate drive output 2 for the second synchronous rectifier MOSFET, internally clamped with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended especially when MOSFETs are paralleled.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	SOP-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (Absolute Maximum)	VCC	-0.3		20	V		5
Cont. Drain Sense Voltage	VD	-3		200	V		5
Pulse Drain Sense Voltage	VD	-5		200	V		5
Source Sense Voltage	VS	-3		20	V		5
Gate Voltage	VGATE	-0.3		20	V	VCC=20V, Gate off	5
Operating Junction Temperature	TJ	-40		150	°C		5
Storage Temperature	TS	-55		150	°C		5
Switching Frequency	fsw			500	kHz		5
Supply Voltage Operating Range	VCC	8.6		18	V	GBD	6
Junction Temperature Range (electrical characteristics)	TJ	-25		125	°C	Specified supply voltage and junction temperature range	6
VCC Turn On Threshold	VCC ON	7.5	8.1	8.5	V		6
VCC Turn Off Threshold (Under Voltage Lock Out)	VCC UVLO	7	7.6	8	V		6
Operating Current	ICC		14	18	mA	CLOAD =1nF, fSW = 400kHz	6
Operating Current	ICC		48	60	mA	CLOAD =4.7nF, fSW = 400kHz	6
Quiescent Current	IQCC		2.6	3.8	mA		6
Turn-off Threshold	VTH1	-12	-6	0	mV		6
Turn-on Threshold	VTH2	-220	-140	-80	mV		6
Input Bias Current	IIBIAS1		1	10	µA	VD = -50mV	6
Input Bias Current	IIBIAS2		10	50	µA	VD = 200V	6
Blanking pulse duration	tBLANK	9	17	25	µs		6
Minimum on time	TONmin	500	750	1000	ns		6
Gate Low Voltage	VGLO		0.3	0.5	V	IGATE = 200mA	7
Gate High Voltage	VGTH	8.5	10.7	13.5	V	VCC=12V-18V (internally clamped)	7
Turn on Propagation Delay	tDon		60	120	ns	VDS to VGATE -100mV overdrive	7
Turn off Propagation Delay	tDoff		70	120	ns	VDS to VGATE -100mV overdrive	7
Package Power Dissipation	PD		970		mW	SOIC-8, TAMB=25°C	5
Thermal Resistance	RθJA		128		°C/W	SOIC-8	5
VCC Turn On/Off Hysteresis	VCC HYST		0.5		V		6
Start-up Current	ICC START		140		µA	VCC=VCC ON - 0.1V	6
Comparator Hysteresis	VHYST		141		mV		6
Comparator Input Offset	VOFFSET		2		mV	GBD	6
Reset Threshold	VTH3		2.5		V	VCC=10V, GBD	6
Reset Threshold	VTH3		5.4		V	VCC=20V, GBD	6
One-shot Hysteresis	VHYST3		40		mV	VCC=10V - GBD	6
Rise Time	tr1		10		ns	CLOAD = 1nF	7
Rise Time	tr2		80		ns	CLOAD = 4.7nF	7
Fall Time	tf1		5		ns	CLOAD = 1nF	7
Fall Time	tf2		25		ns	CLOAD = 4.7nF	7
Pull up Resistance	rup		5		Ω	IGATE = 15mA - GBD	7
Pull down Resistance	rdown		1.2		Ω	IGATE = -200mA	7
Output Peak Current (source)	IO source		1		A	CLOAD = 1nF - GBD	7
Output Peak Current (sink)	IO sink		4		A	CLOAD = 1nF - GBD	7

CAD (KiCad official)

Symbol: IR1168STRPBF
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: ir1168strpbf-etched.step / ir1168strpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ir1168strpbf.step / ir1168strpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (22 pp, sha256 87bc8061abf9c3ee, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF