IR11682STRPBF

{
  "slug": "ir11682strpbf",
  "version": "0.1.0",
  "type": "component",
  "description": "Infineon Technologies AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "ir11682strpbf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ir11682strpbf.kicad_sym",
    "ir11682strpbf.kicad_mod",
    "ir11682strpbf.glb",
    "ir11682strpbf.step",
    "ir11682strpbf.lbr",
    "docs/hero.png",
    "docs/ir11682strpbf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ir11682strpbf-hero.glb",
    "ir11682strpbf-hero.overlay.json",
    "ir11682strpbf-etched.glb"
  ],
  "component": {
    "mpn": "IR11682STRPBF",
    "manufacturer": "Infineon Technologies",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management (PMIC)",
    "subcategory": "AC-DC Controllers And Regulators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883791774928896",
    "parts": {
      "symbol": "ir11682strpbf.kicad_sym",
      "footprint": "ir11682strpbf.kicad_mod",
      "model_3d": "ir11682strpbf-hero.glb",
      "model_3d_plain": "ir11682strpbf-etched.glb",
      "model_3d_step": "ir11682strpbf-etched.step",
      "model_3d_step_plain": "ir11682strpbf.step",
      "lbr": "ir11682strpbf.lbr"
    },
    "distributor_links": {
      "lcsc": "C148145"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T09:44:18Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "GATE1",
        "type": "output",
        "description": "Gate drive output 1 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled."
      },
      {
        "number": "2",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage pin monitored by the UVLO circuit, operating range 8.6 V to 18 V (absolute maximum 20 V), and it is not internally clamped."
      },
      {
        "number": "3",
        "name": "VS1",
        "type": "input",
        "description": "Differential source voltage sense for sync FET 1, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7)."
      },
      {
        "number": "4",
        "name": "VD1",
        "type": "input",
        "description": "High-voltage drain voltage sense for sync FET 1, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V."
      },
      {
        "number": "5",
        "name": "VD2",
        "type": "input",
        "description": "High-voltage drain voltage sense for sync FET 2, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V."
      },
      {
        "number": "6",
        "name": "VS2",
        "type": "input",
        "description": "Differential source voltage sense for sync FET 2, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7)."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Analog and power ground; the internal circuitry and gate drivers are referenced to this pin, and output voltage and current parameters are referenced to it."
      },
      {
        "number": "8",
        "name": "GATE2",
        "type": "output",
        "description": "Gate drive output 2 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The ordering table (page 22) lists IR11682STRPBF as the Tape and Reel (2500 pcs) version of the SOIC; Pin electrical types are not stated in the datasheet; they were assigned from the pin functions (gat; Pin descriptions include the recommended-operation limits from the datasheet. The VD1/VD2 range of -",
          "2/8 pins cited to the wrong page (name found elsewhere): ['1:GATE1@p11', '8:GATE2@p11']"
        ],
        "pages_sent": 22,
        "cost_usd": 0.0536,
        "at": "2026-10-18T09:42:43"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883791774928896",
        "pages": 22,
        "sha256": "3bf27dddd527a722",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ir11682strpbf.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ir11682strpbf-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "a20061156adc4c6e88ef5d5641836481b05893512e1348bcbb203649b585b60a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}