component
IR11682STRPBF
Public Made by Adomby adom
Infineon Technologies AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
IR11682STRPBF
Infineon Technologies · AC-DC Controllers And Regulators · SOIC-8
IR11682STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE1 | output | Gate drive output 1 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled. |
| 2 | VCC | power_in | Supply voltage pin monitored by the UVLO circuit, operating range 8.6 V to 18 V (absolute maximum 20 V), and it is not internally clamped. |
| 3 | VS1 | input | Differential source voltage sense for sync FET 1, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7). |
| 4 | VD1 | input | High-voltage drain voltage sense for sync FET 1, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V. |
| 5 | VD2 | input | High-voltage drain voltage sense for sync FET 2, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V. |
| 6 | VS2 | input | Differential source voltage sense for sync FET 2, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7). |
| 7 | GND | power_in | Analog and power ground; the internal circuitry and gate drivers are referenced to this pin, and output voltage and current parameters are referenced to it. |
| 8 | GATE2 | output | Gate drive output 2 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.3 | 20 | V | 5 | ||
| Cont. Drain Sense Voltage | VD | -1 | 200 | V | 5 | ||
| Pulse Drain Sense Voltage | VD | -5 | 200 | V | 5 | ||
| Source Sense Voltage | VS | -3 | 20 | V | 5 | ||
| Gate Voltage | VGATE | -0.3 | 20 | V | VCC=20V, Gate off | 5 | |
| Operating Junction Temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage Temperature | TS | -55 | 150 | °C | 5 | ||
| Thermal Resistance | RθJA | 128 | °C/W | SOIC-8 | 5 | ||
| Package Power Dissipation | PD | 970 | mW | SOIC-8, TAMB=25°C | 5 | ||
| Switching Frequency | fsw | 400 | kHz | 5 | |||
| VCC Supply voltage | VCC | 8.6 | 18 | V | 5 | ||
| Drain Sense Voltage | VD1, VD2 | -3 | 200 | V | VD1, VD2 -3V negative spike width ≤100ns | 5 | |
| Junction Temperature | TJ | -25 | 125 | °C | 5 | ||
| Switching Frequency | Fsw | 400 | kHz | 5 | |||
| Supply Voltage Operating Range | VCC | 8.6 | 18 | V | 6 | ||
| VCC Turn On Threshold | VCC ON | 7.5 | 8.1 | 8.5 | V | 6 | |
| VCC Turn Off Threshold | VCC UVLO | 7 | 7.6 | 8 | V | 6 | |
| Turn-off Threshold | VTH1 | -12 | -6 | 0 | mV | 6 | |
| Turn-on Threshold | VTH2 | -220 | -140 | -80 | mV | 6 | |
| Blanking pulse duration | tBLANK | 8 | 17 | 25 | µs | 6 | |
| Minimum on time | TOnmin | 600 | 850 | 1100 | ns | 6 | |
| Gate High Voltage | VGTH | 8.5 | 10.7 | 13.5 | V | VCC=12V-18V (internally clamped) | 7 |
CAD (KiCad official)
- Symbol:
IR11682STRPBF - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ir11682strpbf-etched.step/ir11682strpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ir11682strpbf.step/ir11682strpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (22 pp, sha256
3bf27dddd527a722, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IR11682STRPBF
**Infineon Technologies** · AC-DC Controllers And Regulators · SOIC-8
IR11682STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE1 | output | Gate drive output 1 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled. |
| 2 | VCC | power_in | Supply voltage pin monitored by the UVLO circuit, operating range 8.6 V to 18 V (absolute maximum 20 V), and it is not internally clamped. |
| 3 | VS1 | input | Differential source voltage sense for sync FET 1, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7). |
| 4 | VD1 | input | High-voltage drain voltage sense for sync FET 1, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V. |
| 5 | VD2 | input | High-voltage drain voltage sense for sync FET 2, rated -3 V to 200 V recommended (-3 V spikes limited to 100 ns), with a 1 kΩ to 2 kΩ series resistor recommended when VD exceeds 100 V. |
| 6 | VS2 | input | Differential source voltage sense for sync FET 2, which must be Kelvin-connected as close as possible to the MOSFET source pin and must not be tied directly to GND (pin 7). |
| 7 | GND | power_in | Analog and power ground; the internal circuitry and gate drivers are referenced to this pin, and output voltage and current parameters are referenced to it. |
| 8 | GATE2 | output | Gate drive output 2 is internally clamped (10.7 V typ.) with +1 A source / -4 A sink peak drive capability, and a gate resistor is recommended, especially when MOSFETs are paralleled. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.3 | | 20 | V | | 5 |
| Cont. Drain Sense Voltage | VD | -1 | | 200 | V | | 5 |
| Pulse Drain Sense Voltage | VD | -5 | | 200 | V | | 5 |
| Source Sense Voltage | VS | -3 | | 20 | V | | 5 |
| Gate Voltage | VGATE | -0.3 | | 20 | V | VCC=20V, Gate off | 5 |
| Operating Junction Temperature | TJ | -40 | | 150 | °C | | 5 |
| Storage Temperature | TS | -55 | | 150 | °C | | 5 |
| Thermal Resistance | RθJA | | | 128 | °C/W | SOIC-8 | 5 |
| Package Power Dissipation | PD | | | 970 | mW | SOIC-8, TAMB=25°C | 5 |
| Switching Frequency | fsw | | | 400 | kHz | | 5 |
| VCC Supply voltage | VCC | 8.6 | | 18 | V | | 5 |
| Drain Sense Voltage | VD1, VD2 | -3 | | 200 | V | VD1, VD2 -3V negative spike width ≤100ns | 5 |
| Junction Temperature | TJ | -25 | | 125 | °C | | 5 |
| Switching Frequency | Fsw | | | 400 | kHz | | 5 |
| Supply Voltage Operating Range | VCC | 8.6 | | 18 | V | | 6 |
| VCC Turn On Threshold | VCC ON | 7.5 | 8.1 | 8.5 | V | | 6 |
| VCC Turn Off Threshold | VCC UVLO | 7 | 7.6 | 8 | V | | 6 |
| Turn-off Threshold | VTH1 | -12 | -6 | 0 | mV | | 6 |
| Turn-on Threshold | VTH2 | -220 | -140 | -80 | mV | | 6 |
| Blanking pulse duration | tBLANK | 8 | 17 | 25 | µs | | 6 |
| Minimum on time | TOnmin | 600 | 850 | 1100 | ns | | 6 |
| Gate High Voltage | VGTH | 8.5 | 10.7 | 13.5 | V | VCC=12V-18V (internally clamped) | 7 |
## CAD (KiCad official)
- Symbol: `IR11682STRPBF`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ir11682strpbf-etched.step` / `ir11682strpbf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ir11682strpbf.step` / `ir11682strpbf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883791774928896) (22 pp, sha256 `3bf27dddd527a722`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ir11682strpbf-datasheet.pdf)