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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

IPS4260L

STMicroelectronics · Power Distribution Switches · HTSSOP-20-EP

IPS4260L from STMicroelectronics, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PGND	power_in	Integrated power switch ground, internally connected to source of integrated switches; part of multi-pin ground connection.
2	PGND	power_in	Integrated power switch ground, internally connected to source of integrated switches; part of multi-pin ground connection.
3	VZ	output	Load clamp voltage pin, must be shorted to pin 18 and connected directly to supply rail or via external Zener/TVS diode; clamps inductive load turn-off transients; voltage range -0.3 V to 55 V.
4	IN1	bidirectional	Channel 1 input/control with internal weak pull-down resistor; internally wired to open drain diagnostic transistor for cut-off and thermal shutdown signaling; input voltage range 0 V to 5.5 V.
5	IN2	bidirectional	Channel 2 input/control with internal weak pull-down resistor; internally wired to open drain diagnostic transistor for cut-off and thermal shutdown signaling; input voltage range 0 V to 5.5 V.
6	IN3	bidirectional	Channel 3 input/control with internal weak pull-down resistor; internally wired to open drain diagnostic transistor for cut-off and thermal shutdown signaling; input voltage range 0 V to 5.5 V.
7	IN4	bidirectional	Channel 4 input/control with internal weak pull-down resistor; internally wired to open drain diagnostic transistor for cut-off and thermal shutdown signaling; input voltage range 0 V to 5.5 V.
8	SGND	power_in	Logic interface block ground, provides reference level for logic interface and must be shorted to PGND on application board to minimize switching noise.
9	OL	tri_state	Cumulative open load diagnostic output, open drain pin activated when any load is disconnected in off-state; output voltage 0.1 V at 5 mA; current range -10 mA to +10 mA.
10	FLT	tri_state	Common cut-off and thermal shutdown fault diagnostic output, open drain pin; activated during thermal shutdown or current limitation cut-off event on any channel; output voltage 0.1 V at 5 mA.
11	CoD	input	Cut-off delay programming input, cannot be left floating; connect to SGND to disable cut-off function or connect external resistor (60-240 kΩ range) to set cut-off delay; voltage range 0 V to 5.5 V.
12	ILIM	input	Current limitation threshold programming input, cannot be left floating; connect external resistor (30-120 kΩ) between pin and SGND to set current limit threshold; voltage range 0 V to 5.5 V.
13	VCC	power_in	Supply voltage input with operating range 8 V to 50 V; absolute maximum rating 55 V; must be connected directly to supply rail; includes internal undervoltage lock-out.
14	LOAD4	output	Channel 4 power stage output, low-side switch output; load connected between this pin and VCC rail; output voltage range -0.3 V to VDEMAG (55-60 V); current limited by ILIM setting.
15	LOAD3	output	Channel 3 power stage output, low-side switch output; load connected between this pin and VCC rail; output voltage range -0.3 V to VDEMAG (55-60 V); current limited by ILIM setting.
16	LOAD2	output	Channel 2 power stage output, low-side switch output; load connected between this pin and VCC rail; output voltage range -0.3 V to VDEMAG (55-60 V); current limited by ILIM setting.
17	LOAD1	output	Channel 1 power stage output, low-side switch output; load connected between this pin and VCC rail; output voltage range -0.3 V to VDEMAG (55-60 V); current limited by ILIM setting.
18	VZ	output	Load clamp voltage pin, must be shorted to pin 3 and connected directly to supply rail or via external Zener/TVS diode; clamps inductive load turn-off transients; voltage range -0.3 V to 55 V.
19	PGND	power_in	Integrated power switch ground, internally connected to source of integrated switches; part of multi-pin ground connection.
20	PGND	power_in	Integrated power switch ground, internally connected to source of integrated switches; part of multi-pin ground connection.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-20-EP
Category	Power Management (PMIC)
Pins	21

CAD (KiCad official)

Symbol: IPS4260L
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: ips4260l-etched.step / ips4260l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ips4260l.step / ips4260l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (28 pp, sha256 5455c0377292d727, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF