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IPP200N15N3G

Public Made by Adom

by adom

Infineon Technologies MOSFETs, TO-220-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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IPP200N15N3G

Infineon Technologies · MOSFETs · TO-220-3

IPP200N15N3G from Infineon Technologies, in a TO-220-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate pin; gate-source voltage limited to ±20 V, with threshold VGS(th) of 2 V min to 4 V max at 90 µA.
2 D passive Drain pin, also connected to the mounting tab; rated for 150 V VDS and 50 A continuous drain current at TC=25 °C.
3 S passive Source pin; carries up to 50 A continuous current and the body diode continuous forward current of 50 A.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-220-3
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Continuous drain current ID 50 A TC=25 °C 1
Continuous drain current ID 40 A TC=100 °C 1
Pulsed drain current ID,pulse 200 A TC=25 °C 1
Avalanche energy, single pulse EAS 170 mJ ID=50 A, RGS=25 W 1
Reverse diode dv/dt dv/dt 6 kV/µs ID=50 A, VDS=120 V, di/dt=100 A/µs, Tj,max=175 °C 1
Gate source voltage VGS -20 20 V 1
Power dissipation Ptot 150 W TC=25 °C 1
Operating and storage temperature Tj, Tstg -55 175 °C 1
Thermal resistance, junction - case RthJC 1 K/W 2
Thermal resistance, junction - ambient RthJA 75 K/W minimal footprint 2
Thermal resistance, junction - ambient RthJA 50 K/W 6 cm2 cooling area 2
Drain-source breakdown voltage V(BR)DSS 150 V VGS=0 V, ID=1 mA 2
Gate threshold voltage VGS(th) 2 3 4 V VDS=VGS, ID=90 µA 2
Zero gate voltage drain current IDSS 0.1 1 µA VDS=120 V, VGS=0 V, Tj=25 °C 2
Zero gate voltage drain current IDSS 10 100 µA VDS=120 V, VGS=0 V, Tj=125 °C 2
Gate-source leakage current IGSS 1 100 nA VGS=20 V, VDS=0 V 2
Drain-source on-state resistance RDS(on) 16 20 mW VGS=10 V, ID=50 A 2
Transconductance gfs 29 57 S /VDS/>2/ID/RDS(on)max, ID=50 A 2
Turn-on delay time td(on) 14 21 ns VDD=75 V, VGS=10 V, ID=50 A, RG,ext=1.6 W 3
Rise time tr 11 17 ns VDD=75 V, VGS=10 V, ID=50 A, RG,ext=1.6 W 3
Turn-off delay time td(off) 23 35 ns VDD=75 V, VGS=10 V, ID=50 A, RG,ext=1.6 W 3
Fall time tf 6 9 ns VDD=75 V, VGS=10 V, ID=50 A, RG,ext=1.6 W 3
Gate to source charge Qgs 10 14 nC VDD=75 V, ID=50 A, VGS=0 to 10 V 3
Gate to drain charge Qgd 4 6 nC VDD=75 V, ID=50 A, VGS=0 to 10 V 3
Switching charge Qsw 9 13 nC VDD=75 V, ID=50 A, VGS=0 to 10 V 3
Gate charge total Qg 23 31 nC VDD=75 V, ID=50 A, VGS=0 to 10 V 3
Output charge Qoss 60 79 nC VDD=75 V, VGS=0 V 3
Diode continuous forward current IS 50 A 3
Diode pulse current IS,pulse 220 A 3
Diode forward voltage VSD 1 1.2 V VGS=0 V, IF=50 A, Tj=25 °C 3
Input capacitance Ciss 1820 pF VGS=0 V, VDS=75 V, f=1 MHz 3
Output capacitance Coss 214 pF VGS=0 V, VDS=75 V, f=1 MHz 3
Reverse transfer capacitance Crss 5 pF VGS=0 V, VDS=75 V, f=1 MHz 3
Gate plateau voltage Vplateau 5.7 V VDD=75 V, ID=50 A, VGS=0 to 10 V 3
Gate resistance RG 2.4 W 2
Reverse recovery time trr 106 ns VR=75 V, IF=IS, diF/dt=100 A/µs, TC=25 °C 3
Reverse recovery charge Qrr 332 nC VR=75 V, IF=IS, diF/dt=100 A/µs, TC=25 °C 3

CAD (KiCad official)

  • Symbol: IPP200N15N3G
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220-3 (KiCad packages3D, STEP)
  • 3D model files: ipp200n15n3g-etched.step / ipp200n15n3g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ipp200n15n3g.step / ipp200n15n3g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (12 pp, sha256 d4924d66c7ee9886, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF