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IPD135N03LG

Infineon Technologies · MOSFETs · TO-252

IPD135N03LG from Infineon Technologies, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate (pin 1) of the N-channel logic-level MOSFET; gate-source voltage limited to ±20 V, threshold 1 V min to 2.2 V max.
2 D passive Drain (pin 2), also connected to the tab; VDS max 30 V and continuous drain current 30 A at VGS=10 V, TC=25 °C.
3 S passive Source (pin 3) of the N-channel MOSFET; RDS(on) is measured from drain tab to source pin, 13.5 mΩ max at VGS=10 V, ID=30 A.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-252
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: IPD135N03LG
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: ipd135n03lg-etched.step / ipd135n03lg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ipd135n03lg.step / ipd135n03lg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (12 pp, sha256 31d4953ffa0a65c6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF