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IP808AR

Public Made by Adom

by adom

IC Plus Ethernet ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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IP808AR

IC Plus · Ethernet ICs · QFN-48-EP(7x7)

IP808AR from IC Plus, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground.
2 ALT_A/B input Latched upon power-on reset to define ALT_A/ALT_B type: 1 = ALT_A (default), 0 = ALT_B.
3 PortN0 input Port 0 negative feeding voltage input.
4 AGND power_in Analog ground.
5 PortN1 input Port 1 negative feeding voltage input.
6 AGND power_in Analog ground.
7 NC unconnected No connection.
8 PortN2 input Port 2 negative feeding voltage input.
9 AGND power_in Analog ground.
10 PortN3 input Port 3 negative feeding voltage input (table text reads 'Port0', apparent typo).
11 AGND power_in Analog ground.
12 AGND power_in Analog ground.
13 SCAN0 input Operation mode select input, see section 5.2 Table 2.
14 SCAN1 input Operation mode select input, see Table 2; must be connected to AGND for normal operation.
15 Vrext passive Connect to RGND through a 62kΩ ±1% resistor; for internal bias only.
16 RGND power_in Low noise analog reference ground, to be connected to AGND.
17 V54 power_in Main power supply input for the chip; add a 1uF capacitor between V54 and AGND.
18 AGND power_in Analog ground.
19 V5 power_out Internal 5V generation for internal use only; add a 4.7uF capacitor between V5 and AGND.
20 V3P3 power_out 3.3V rail: with EnB_Reg at AGND the built-in regulator supplies 3.3V (6mA) to external devices; with EnB_Reg at 3.3V it must be fed from external 3.3V (6mA minimum); add a 4.7uF capacitor to AGND.
21 V1P8 power_out Internal 1.8V for internal use only; add a 1uF capacitor between V1P8 and AGND.
22 VPP power_in Connect to V5 for EFuse power.
23 In_Top power_in Must be connected to AGND for normal operation.
24 EnB_Reg input Enables/disables the internal 3.3V regulator (AGND = regulator active, 3.3V = disabled); see V3P3.
25 AGND power_in Analog ground.
26 AGND power_in Analog ground.
27 PortN4 input Port 4 negative feeding voltage input.
28 AGND power_in Analog ground.
29 PortN5 input Port 5 negative feeding voltage input.
30 NC unconnected No connection.
31 AGND power_in Analog ground.
32 PortN6 input Port 6 negative feeding voltage input.
33 AGND power_in Analog ground.
34 PortN7 input Port 7 negative feeding voltage input.
35 NC unconnected No connection.
36 AGND power_in Analog ground.
37 LED_CLK output Open-drain serial LED clock output, see section 5.10 LED interface.
38 LED_DAT output Open-drain serial LED data output, direct to Overload LED.
39 SCL/EE_CLK bidirectional Open-drain I2C clock input in manual mode; clock output to EEPROM in auto mode.
40 SDAO output Open-drain I2C serial data output.
41 SDAI/EE_DAT bidirectional Open-drain I2C serial data input in manual mode; data input from EEPROM in auto mode.
42 INTB output Open-drain active-low interrupt output.
43 DGND power_in Digital ground, to be connected to AGND.
44 DV3P3 power_in Digital 3.3V power; add a 4.7uF capacitor to DGND and connect to V3P3.
45 RstN input Active-low reset input for IP808AR.
46 AD2 input I2C device address bit 2, latched upon reset.
47 AD1 input I2C device address bit 1, latched upon reset.
48 AD0 input I2C device address bit 0, latched upon reset.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer IC Plus
Package QFN-48-EP(7x7)
Category Interface ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage V54-AGND V54 -0.3 75 V V54, AGND 46
PortNn-AGND PortNn -0.3 75 V PortNn, AGND @n=0~7 46
V5 voltage V5 -0.3 5.5 V V5, AGND 46
All other pins -0.3 3.6 V All other Pin, (AGND, or DGND) 46
DGND-AGND RGND, AGND -0.3 0.3 V DGND, AGND 46
Maximum Junction Temperature 150 ℃ 46
Storage Temperature Range -65 150 ℃ 46
Lead Temperature 260 ℃ 30s, reflow 46
ESD at all pins 2 KV HBM ±2 KV 46
Ambient temperature Ta -40 85 ℃ 46
V54 supply @ AF V54 44 48 57 V V54, AGND @ AF 46
V54 supply @ AT V54 50 54 57 V V54, AGND @ AT 46
V54 Power Supply voltage AF V54 44 57 V 45V~57V @AF 46
V54 Power Supply voltage AT V54 50 57 V 51V~57V @AT 46
V54 operating current I54 8 15 mA All ports on @w/o peripheral load current & port load current 46
V3P3 voltage V3P3 3.13 3.3 3.46 V External Capacitance=4.7uF, V3P3 short DV3P3 46
V3P3 output current Iout_v3p3 6 mA EnB_Reg=low V3P3 providing to peripheral device, V3P3 short DV3P3 46
V3P3 input current Iin_v3p3 6 mA EnB_Reg=high External 3.3V provides to V3P3, V3P3 short DV3P3 46
V5 internal V5 4.99 5.25 5.51 V External Capacitance=4.7uF 46
V1P8 internal V1P8 1.71 1.8 1.89 V External Capacitance=1uF 46
V54 UVLO rising V54_UVL 30 V Rising V54, AGND 46
V54 UVLO falling V54_UVL 27 V Falling V54, AGND 46
V54 OVLO rising V54_OVL 63 V Rising V54, AGND 46
V54 OVLO falling V54_OVL 60 V Falling V54, AGND 46
V3P3 rise release V3P3_Rise 2.8 V Rising V3P3, AGND, V3P3 short DV3P3 46
V3P3 fall reset V3P3_Fall 1.9 V Falling V3P3, AGND, V3P3 short DV3P3 46
Overload auto-recovery time Tovlrec 1.6 s From overload shutdown to next detection 47
Imin_off auto-recovery time Tudlrec 1.6 s From Imin_off shutdown to next detection 47
Back-off time Tbackoff 2.5 s Midspan mode detection back-off time 47
Inrush current Iinrush 400 425 450 mA For t=50ms Cload=180uF max. 47
Port off current Imin_off 0 5 mA Must disconnect for t greater than Tmpdo 47
Port off or on current Imin_onoff 5 7.5 10 mA May or may not disconnect for greater than Tmpdo 47
PD maintenance power signature dropout time Tmpdo 300 310 400 ms AF/AT 47
PD maintenance power signature time for validity Tmps 6 ms Port current pulse width to reset disconnect timer 47
Over load current AF Icut 350 375 400 mA AF@Vport=44V (default) 47
Over load current AT Icut 600 640 664 mA AT@Vport=50V (default) 47
Max over load current Class 0 Icut 350 375 400 mA Class 0, Vport=44V 47
Max over load current Class 1 Icut 91 112 133 mA Class 1, Vport=44V 47
Max over load current Class 2 Icut 160 206 252 mA Class 2, Vport=44V 47
Max over load current Class 3 Icut 350 375 400 mA Class 3, Vport=44V 47
Max over load current Class 4 Icut 600 640 680 mA Class 4, Vport=50V 47
Over load time Tcut 50 62.5 75 ms Iport > Icut, AF/AT 47
Current limit AF Ilim 400 425 450 mA AF@Vport=44V 47
Current limit AT Ilim 800 860 920 mA AT@Vport=50V 47
Current limit time Tlim 50 62.5 75 ms Iport = Ilim, AF/AT 47
Turn off time Toff 500 ms From VportN to V54-2.8V 47
Port on resistance Ron 0.25 Ω Iport ≦ 640mA & Ta=25℃ 47
PortN leakage current Ioff_port 10 uA V54=54V , Ta=25℃, Port off 47
Classification current Class 0 Iclass 0 5 mA Class 0 49
Classification current Class 1 Iclass 8 13 mA Class 1 49
Classification current Class 2 Iclass 16 21 mA Class 2 49
Classification current Class 3 Iclass 25 31 mA Class 3 49
Classification current Class 4 Iclass 35 45 mA Class 4 49
Mark voltage Vmark 7 9 10 V V54, PortNn, (n=0~7) @0mA ≦ Imark ≦ 10mA 49
Mark current limitation Imarklim 5 100 mA V54=PortNn, (n=0~7) 49
Classification event time Tcle 6 12 30 ms Width for classification event 1 or event 2 49
Mark event 1 time Tme1 6 9 12 ms Width for mark event 1 49
Mark event 2 time Tme2 16 22 ms Width for mark event 2 49
Power turn on time Tpon 55 400 ms From end of valid detect to application of power to port 49
Thermal shutdown Tsd 150 ℃ Internal temperature for thermal shutdown 49
Thermal shutdown hysteresis Thy 129 ℃ Internal temperature for release thermal shutdown 49
Input low voltage I2C VIL 0.8 V SCL/EE_CLK,SDAI/EE_DAT@ I2C mode, SCAN0, SCAN1 50
Input high voltage I2C VIH 2.2 V SCL/EE_CLK,SDAI/EE_DAT@I2C mode, SCAN0, SCAN1 50
Open drain output low voltage (auto mode) VOL 0.7 V SCL/EE_CLK,SDAI/EE_DAT@auto mode @ Isink =5mA 50
Open drain output low voltage VOL 0.7 V SDAO,INTB,LED_CLK,LED_DAT @ Isink =5mA 50
Input low voltage AD0~AD2 VIL 0.8 V AD0~AD2 50
Input high voltage AD0~AD2 VIH 2.2 V AD0~AD2 50

CAD (KiCad official)

  • Symbol: IP808AR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ip808ar-etched.step / ip808ar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ip808ar.step / ip808ar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: IC Plus datasheet (55 pp, sha256 b266e4654a89bc82, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF