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IP804AR

Public Made by Adom

by adom

IC Plus Ethernet Transceivers, QFN-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

markdown

IP804AR

IC Plus · Ethernet Transceivers · QFN-48(7x7)

IP804AR from IC Plus, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground connection.
2 NC unconnected No connection.
3 PortN0 bidirectional Port 0 return pin for the power interface carrying negative side of PoE supply path.
4 NC unconnected No connection.
5 PortN1 bidirectional Port 1 return pin for the power interface carrying negative side of PoE supply path.
6 AGND power_in Analog ground connection.
7 NC unconnected No connection.
8 PortN2 bidirectional Port 2 return pin for the power interface carrying negative side of PoE supply path.
9 NC unconnected No connection.
10 PortN3 bidirectional Port 3 return pin for the power interface carrying negative side of PoE supply path.
11 AGND power_in Analog ground connection.
12 AGND power_in Analog ground connection.
13 SCAN0 input Operation mode selection pin; refer to section 5.2 table 2 for mode configuration.
14 SCAN1 input Operation mode selection pin latched at reset; must be connected to AGND for normal operation.
15 Vrext unconnected Internal use only, no connection required.
16 NC unconnected No connection.
17 V54 power_in Main power supply input (44V to 57V) requiring 1µF and 47µF/100V capacitors to AGND.
18 NC unconnected No connection.
19 V5 power_in Internal 5V power supply for internal use only; add 4.7µF capacitor to AGND.
20 V3P3 power_in 3.3V power supply providing up to 6mA external device current when EnB_Reg is low, or external 3.3V input when EnB_Reg is high; add 4.7µF capacitor to AGND.
21 V1P8 power_in Internal 1.8V power supply for internal use only; add 4.7µF capacitor to AGND.
22 VPP power_in eFuse power supply pin connected to V5.
23 In_Top power_in Bias current source pin that must be connected to AGND for normal operation.
24 EnB_Reg input Enable/Disable control for internal 3.3V regulator selecting between active regulation or external 3.3V supply.
25 AGND power_in Analog ground connection.
26 AGND power_in Analog ground connection.
27 AGND power_in Analog ground connection.
28 ALT_A/B input Alternative A/B type selection pin latched at power-on reset (0=ALT_A default, 1=ALT_B) to define wiring configuration.
29 24V_En input 24V enable pin latched at power-on reset (0=disable default, 1=enable) for 24V low voltage applications.
30 4Pair_En input 4-Pair high power mode enable pin latched at power-on reset (0=disable default, 1=enable).
31 AGND power_in Analog ground connection.
32 P0LED output Direct LED output for Port 0 status indication.
33 P1LED output Direct LED output for Port 1 status indication.
34 P2LED output Direct LED output for Port 2 status indication.
35 P3LED output Direct LED output for Port 3 status indication.
36 Overload output Direct LED output for system overload or temperature warning indication.
37 LED_CLK tri_state Serial LED clock output as open-drain; refer to section 5.11 for LED interface details.
38 LED_DAT tri_state Serial LED data output as open-drain.
39 SCL/EE_CLK tri_state I2C clock input in manual mode or EEPROM clock output in auto mode as open-drain.
40 SDAO tri_state I2C serial data output as open-drain.
41 SDAI/EE_DAT tri_state I2C serial data input in manual mode or EEPROM data input in auto mode.
42 INTB tri_state Interrupt output as open-drain and active low.
43 DGND power_in Digital ground connection that must be connected to AGND.
44 DV3P3 power_in Digital 3.3V power requiring 4.7µF capacitor to DGND and connection to V3P3.
45 RstN input Active-low reset input signal to reset IP804AR.
46 AD2 input I2C device address selection bit 2 latched at power-on reset per section 5.3.
47 AD1 input I2C device address selection bit 1 latched at power-on reset per section 5.3.
48 AD0 input I2C device address selection bit 0 latched at power-on reset per section 5.3.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer IC Plus
Package QFN-48(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: IP804AR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ip804ar-etched.step / ip804ar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ip804ar.step / ip804ar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: IC Plus datasheet (59 pp, sha256 eddd34f0b55a6cd4, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF