IP6525T_N

@@ -0,0 +1,48 @@+# IP6525T_N++**INJOINIC IP6525T N** · DC-DC Converters · ESOP-8++IP6525T_N from INJOINIC IP6525T N, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Power ground. Return path for the internal power stage; must be tied to the exposed pad (EPAD) plane for proper thermal and electrical performance. |+| 2 | SW | output | DCDC switching node. Connects to the external buck inductor. Absolute-max SW voltage range is -0.3 V to 40 V. |+| 3 | BST | passive | Bootstrap pin for the high-side gate driver. Connect a bootstrap capacitor between BST and SW (placed close to the IC) to provide the drive voltage for the upper power MOSFET gate. |+| 4 | HLED/EN | bidirectional | Dual-function pin. Default configuration is HLED (fast-charge status LED indicator drive); optionally can be configured as an external Enable (EN) input via factory customization. |+| 5 | DM | bidirectional | USB D- (data minus) line used for fast-charge protocol handshaking (DCP/QC2.0/QC3.0/FCP/AFC). Absolute-max voltage range -0.3 V to 30 V. |+| 6 | DP | bidirectional | USB D+ (data plus) line used for fast-charge protocol handshaking (DCP/QC2.0/QC3.0/FCP/AFC). Absolute-max voltage range -0.3 V to 30 V. |+| 7 | VIN | power_in | Input supply pin, 9.6 V to 32 V (absolute-max 40 V). Place a decoupling ceramic capacitor (100 nF recommended) close to the IC. |+| 8 | VOUT | input | Output voltage feedback / sense pin. Used by the internal loop to regulate the buck output (3 V-12 V typical) and provide line-drop compensation (~100 mV @ 1 A). |+| 9 | EPAD | power_in | Exposed thermal pad on the bottom of the ESOP-8 package. Serves as power ground and heatsink; must be soldered to a solid GND copper pour for thermal dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | INJOINIC IP6525T N |+| Package | ESOP-8 |+| Category | PMIC |+| Pins | 9 |++## Ordering variants++- `IP6525T_NIP6525T`++## CAD (KiCad official)++- Symbol: `IP6525T_N`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`+- 3D model: ESOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [INJOINIC IP6525T N datasheet](docs/ip6525t-n-datasheet.pdf) (11 pp, sha256 `1376a6951cb2f147`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ip6525t-n-datasheet.pdf)

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