# IP6523S

**INJOINIC** · Battery Management · ESOP-8

IP6523S from INJOINIC, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage node, rated 8 V to 32 V in normal operation with an absolute maximum range of -0.3 V to 40 V. |
| 2 | UV/EN | input | Input under-voltage setting and chip enable; pulling this pin down shuts down the DC-DC converter, and it must not be connected to VIN because it will be damaged by the high voltage. |
| 3 | DP | bidirectional | USB data terminal for the fast-charge (DCP) protocol; DM/DP voltage is limited to -0.3 V to 6 V absolute maximum. The pin table describes this pin as the DM terminal, so the labelling conflicts with pin 4. |
| 4 | DM | bidirectional | USB data terminal for the fast-charge (DCP) protocol; DM/DP voltage is limited to -0.3 V to 6 V absolute maximum. The pin table describes this pin as the DP terminal, so the labelling conflicts with pin 3. |
| 5 | VOUT | input | Output voltage feedback node for the 5 V output; absolute maximum voltage is -0.3 V to 30 V. |
| 6 | GND | power_in | Power ground. |
| 7 | SW | output | Switching node of the DC-DC converter; absolute maximum voltage is -0.3 V to 40 V. |
| 8 | BST | passive | Bootstrap capacitor node for the high-side gate drive. |
| 9 | GND | power_in | Exposed pad (printed as 9(EPAD)) used as power and thermal ground; it must have good contact with the PCB GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | INJOINIC |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |

## CAD (KiCad official)

- Symbol: `IP6523S`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `ip6523s-etched.step` / `ip6523s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ip6523s.step` / `ip6523s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [INJOINIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590911368180674560) (12 pp, sha256 `d1932969c79721b7`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ip6523s-datasheet.pdf)