# IP6520T_25W_ZM

**INJOINIC** · Power Management - Specialized · ESOP-8

IP6520T_25W_ZM from INJOINIC, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | input | Output voltage feedback pin; the absolute maximum VOUT voltage range is -0.3 to 20 V. |
| 2 | VIN | power_in | Input voltage pin that needs a filter ceramic capacitor placed close to the IC; recommended VIN is 7.3 V to 32 V and the absolute maximum range is -0.3 to 40 V. |
| 3 | SW | output | Power switch node that connects to the external inductor; the absolute maximum SW voltage range is -0.3 to 40 V. |
| 4 | BST | passive | Bootstrap pin that takes a bootstrap capacitor placed close to the BST and LX (SW) pins to provide the high-side MOSFET gate drive voltage. |
| 5 | DM | bidirectional | USB D- signal pin connecting to the DM line of the USB connector; DM/DP voltage absolute maximum is -0.3 to 6 V and DP/DM over-voltage protection trips above 4.5 V. |
| 6 | DP | bidirectional | USB D+ signal pin connecting to the DP line of the USB connector; DM/DP voltage absolute maximum is -0.3 to 6 V and DP/DM over-voltage protection trips above 4.5 V. |
| 7 | CC1 | bidirectional | Type-C detection pin CC1 used to identify the connected device's fast-charge protocol; CC voltage absolute maximum is -0.3 to 15 V and CC over-voltage protection trips above 6.0 V. |
| 8 | CC2 | bidirectional | Type-C detection pin CC2 used to identify the connected device's fast-charge protocol; CC voltage absolute maximum is -0.3 to 15 V and CC over-voltage protection trips above 6.0 V. |
| 9 | PGND | power_in | Exposed pad (EPAD) serving as power ground and heat-sink ground, which must make good contact with the PCB PGND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | INJOINIC |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |

## CAD (KiCad official)

- Symbol: `IP6520T_25W_ZM`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `ip6520t-25w-zm-etched.step` / `ip6520t-25w-zm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ip6520t-25w-zm.step` / `ip6520t-25w-zm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [INJOINIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8560869573014032384) (18 pp, sha256 `73bb1f7645bf2ff5`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ip6520t-25w-zm-datasheet.pdf)