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IP101GA

Public Made by Adom

by adom

IC Plus Ethernet Transceivers, LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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IP101GA

IC Plus · Ethernet Transceivers · LQFP-48(7x7)

IP101GA from IC Plus, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COL/RMII output Collision detection output (active high) or RMII mode selection latched during power-on reset (0=MII, 1=RMII mode).
2 TXEN input Transmit enable input, active high to enable transmission; synchronous with TXCLK.
3 TXD3 input Transmit data bit 3, synchronous to TXCLK (MII 25MHz) or 50M_CLKI (RMII 50MHz).
4 TXD2 input Transmit data bit 2, synchronous to TXCLK (MII 25MHz) or 50M_CLKI (RMII 50MHz).
5 TXD1 input Transmit data bit 1, synchronous to TXCLK (MII 25MHz) or 50M_CLKI (RMII 50MHz).
6 TXD0 input Transmit data bit 0, synchronous to TXCLK (MII 25MHz) or 50M_CLKI (RMII 50MHz).
7 TXCLK/50M_CLKI bidirectional Transmit clock output (25MHz at 100Base-TX, 2.5MHz at 10Base-T) in MII mode; 50MHz clock input required in RMII mode.
8 REGOUT power_in 1.0V regulated output for internal use; requires 10µF and 0.1µF decoupling capacitors for noise filtering.
9 LED0/PHY_AD0 output LED0 output or PHY address bit 0 latched during power-on reset; high impedance reset state.
10 LED1/PHY_AD1 output LED1 output or PHY address bit 1 latched during power-on reset; high impedance reset state.
11 DGND power_in Ground connection for digital circuits.
12 LED2/PHY_AD2 output LED2 output or PHY address bit 2 latched during power-on reset; high impedance reset state.
13 LED3/PHY_AD3 output LED3 output or PHY address bit 3 latched during power-on reset; internal pull-down, high impedance reset state.
14 VDDIO power_in 3.3V or 2.5V digital I/O power supply for LED, RESET_N and MII/RMII interface signals.
15 NC unconnected No connection.
16 RXCLK/50M_CLKO output Receive clock output (25MHz at 100Base-TX, 2.5MHz at 10Base-T) in MII mode; 50MHz clock output in RMII mode.
17 DGND power_in Ground connection for digital circuits.
18 RXD3 output Receive data bit 3 output, high impedance reset state; synchronous to RXCLK (MII) or 50M_CLKO (RMII).
19 RXD2 output Receive data bit 2 output, high impedance reset state; synchronous to RXCLK (MII) or 50M_CLKO (RMII).
20 RXD1 output Receive data bit 1 output, high impedance reset state; synchronous to RXCLK (MII) or 50M_CLKO (RMII).
21 RXD0 output Receive data bit 0 output, high impedance reset state; synchronous to RXCLK (MII) or 50M_CLKO (RMII).
22 RXDV/CRS_DV/FX_HEN output Receive data valid (MII), carrier sense and receive data valid (RMII), or fiber mode select latched during reset (0=TP, 1=fiber); internal pull-down.
23 CRS/LEDMOD output Carrier sense output or LED mode selection latched during reset (0=LED mode 1, 1=LED mode 2); internal pull-down.
24 RXER output Receive error output (high impedance reset state); asserted when decoding error detected or PHY receiving LPI signal.
25 MDC input Management data clock input for serial management interface; maximum clock frequency 2.5MHz.
26 MDIO bidirectional Management data input/output for serial management interface; integrated 250kΩ pull-up resistor.
27 TEST_ON input Test mode enable input with internal pull-down; set high to enable test mode; leave floating for normal operation.
28 ISET input Bandgap circuit current set input; connect to GND via 6.19kΩ ±1% resistor to define internal reference current.
29 AGND1V power_in 1.0V analog circuit ground connection.
30 MDI_RN bidirectional Receive differential pair negative input/output, high impedance reset state; shared by 100Base-TX and 10Base-T modes.
31 MDI_RP bidirectional Receive differential pair positive input/output, high impedance reset state; shared by 100Base-TX and 10Base-T modes.
32 NC unconnected No connection.
33 MDI_TN bidirectional Transmit differential pair negative, high impedance reset state; Manchester code (10Base-T) or MLT-3 (100Base-TX) output.
34 MDI_TP bidirectional Transmit differential pair positive, high impedance reset state; Manchester code (10Base-T) or MLT-3 (100Base-TX) output.
35 AGND33 power_in 3.3V analog circuit ground connection.
36 AVDD33 power_in 3.3V analog power supply for analog circuitry; requires careful decoupling and placed close to chip.
37 NC unconnected No connection.
38 NC unconnected No connection.
39 NC unconnected No connection.
40 NC unconnected No connection.
41 NC unconnected No connection.
42 RESET_N input Active-low reset input with internal pull-up; 25MHz clock must be active 10 cycles before rising edge; device operational 2.5ms after reset release.
43 TXER/FXSD input Transmit error input (TP mode) with internal pull-down; fiber signal detect (fiber mode, 0=down, 1=up); must float or connect to GND in RMII mode.
44 NC unconnected No connection.
45 DGND power_in Ground connection for digital circuits.
46 X1 input 25MHz crystal oscillator input or external 25MHz clock input; connect to GND if using external 50MHz clock on TXCLK/50M_CLKI.
47 X2 output 25MHz crystal oscillator output; leave open when using external oscillator on X1.
48 INTR tri_state Open-drain programmable interrupt output for link status, speed, duplex changes or RX error countdown; requires external pull-up resistor.

Key specifications

Parameter Value
Manufacturer IC Plus
Package LQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: IP101GA
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ip101ga-etched.step / ip101ga-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ip101ga.step / ip101ga.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: IC Plus datasheet (65 pp, sha256 2398538332fea519, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF