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INA500AIDCKR

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Texas Instruments Differential Amplifiers, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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INA500AIDCKR

Texas Instruments · Differential Amplifiers · SC-70-6

INA500AIDCKR from Texas Instruments, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN+ input Non-inverting (positive) input of the difference amplifier, with the common-mode input range set by the gain and REF voltage (for INA500A with VREF = VS/2, 2*(V-) - VREF to 2*(V+) - VREF).
2 V- power_in Negative power supply; the device operates from 1.7 V to 5.5 V single supply (V+ - V-) or ±0.85 V to ±2.75 V dual supply, with 0.1 µF bypass recommended at each supply pin.
3 IN- input Negative (inverting) input of the difference amplifier, which connects to the internal precision matched resistor network.
4 OUT output Amplifier output, referenced to the REF pin voltage; the output swing is limited to within about 10.5 mV of V+ and 8.5 mV of V- at 10 kΩ load (INA500A, page 5), and short-circuit current is continuous-limited to ±33 mA at 5.5 V.
5 REF input Reference input that sets the output mid-level; it must be driven by a low-impedance source (for example a unity-gain buffer) for single-supply operation, and its input voltage range is from V- to V+ at 5.5 V.
6 V+ power_in Positive power supply; the device operates from 1.7 V to 5.5 V single supply (V+ - V-) or ±0.85 V to ±2.75 V dual supply, with 0.1 µF bypass recommended at each supply pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6
Category Amplifiers/Comparators
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, single supply (absolute maximum) VS 6 V single supply, VS = (V+) - (V-) 4
Supply voltage, dual supply (absolute maximum) VS 3 V dual supply, printed as ±3 V 4
Signal input pins current -10 10 mA 4
Operating temperature TA -55 150 °C 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD, human body model (HBM) V(ESD) -2500 2500 V HBM, ANSI/ESDA/JEDEC JS-001, printed ±2500 V 4
ESD, charged device model (CDM) V(ESD) -1500 1500 V CDM, JEDEC JESD22-C101, printed ±1500 V 4
Supply voltage, single supply (recommended) VS 1.7 5.5 V single supply 4
Supply voltage, dual supply (recommended) VS 0.85 2.75 V dual supply, printed as ±0.85 V to ±2.75 V 4
Rated temperature range -40 125 °C 4
Input offset voltage, RTO VOSO -3.5 0.7 3.5 mV VS = 5.5V, TA = 25°C; printed ±0.70 typ, ±3.5 max 5
Input offset voltage over temperature, RTO -3.6 3.6 mV VS = 5.5V, TA = -40°C to 125°C; printed ±3.6 5
Input offset voltage drift, RTO 1.8 8.5 µV/°C VS = 5.5V, TA = -40°C to 125°C; printed typ ±1.8, max 8.5 5
Power supply rejection ratio (PSRR) PSRR 40 175 µV/V VS = 1.7V to 5.5V, TA = 25°C 5
DC common-mode rejection ratio, RTO (high CMRR region) CMRR 75 87 dB VCM from [2*(V-) - VREF] to [2*(V+) - VREF - 1.4V], VS = 5.5V, VREF = VS/2 5
DC common-mode rejection ratio, RTO (rail-to-rail CMRR region) CMRR 62 77 dB VCM from [2*(V-) - VREF] to [2*(V+) - VREF], VS = 5.5V, VREF = VS/2 5
Gain error GE -0.05 0.01 0.05 % VREF = VS/2, VO = (V-) + 0.1V to (V+) - 0.1V; printed ±0.01 typ, ±0.05 max 5
Gain drift over temperature -1 1 ppm/°C TA = -40°C to 125°C; printed ±1 5
Reference gain error REF-GE -0.02 0.005 0.02 % VS = 5.5V; printed ±0.005 typ, ±0.02 max 6
Positive supply rail headroom VOH 10.5 15 mV RL = 10kΩ connected to VS/2 5
Negative supply rail headroom VOL 8.5 15 mV RL = 10kΩ connected to VS/2 5
Short-circuit current ISC -33 33 mA VS = 5.5V; printed ±33 5
Supply voltage, dual supply (electrical table row) VS 0.85 2.75 V dual supply, printed as ±0.85 V to ±2.75 V 6
Quiescent current IQ 13.5 18.5 µA VS = 5.5V 6
Quiescent current over temperature IQ 19.5 µA VS = 5.5V, TA = -40°C to 125°C 6
Junction-to-ambient thermal resistance (DCK, SC70) RθJA 200.2 °C/W 4
Junction-to-case (top) thermal resistance (DCK, SC70) RθJC(top) 127.6 °C/W 4
Junction-to-board thermal resistance (DCK, SC70) RθJB 59.6 °C/W 4
Junction-to-top characterization parameter (DCK, SC70) ψJT 42.6 °C/W 4
Junction-to-board characterization parameter (DCK, SC70) ψJB 59.4 °C/W 4

CAD (KiCad official)

  • Symbol: INA500AIDCKR
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6 (KiCad packages3D, STEP)
  • 3D model files: ina500aidckr-etched.step / ina500aidckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ina500aidckr.step / ina500aidckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 99d0669fe8bf98b6, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF